DC Fault Current Limiter Research Articles

A Voltage-Clamping Type DC Fault Current Limiter With Low Power Losses

A Voltage-Clamping Type DC Fault Current Limiter With Low Power Losses

Novel series LC resonance DC fault current limiter

Novel series LC resonance DC fault current limiter

Two-Stage DC Fault Current Limiter Combining Hybrid Magnetic Materials and Active Flux Coupling Coils

Two-Stage DC Fault Current Limiter Combining Hybrid Magnetic Materials and Active Flux Coupling Coils

Development of a DC hybrid fault-current limiting and interrupting device for microgrid applications with a new approach for current-limiting capability

This research presents the development of a hybrid DC fault current limiter (HDCFCL) for microgrid applications. The proposed HDCFCL configuration comprises two parallel branches; the first is the main circuit, which includes a superconducting material as a current limiting element in series with the auxiliary solid-state switch. The second branch includes the commutation circuit, composed of two groups of ultra-fast turn-off semiconductor switches, IGCTs, connected back-to-back across the absorbing energy branch. A new approach to the current limitation is presented, where a superconducting fault current limiter is used to reduce the short circuit current together with a capacitor to absorb the energy of the commutation circuit during the interrupting process. The PLECS program was used to analyze the results theoretically, and they were verified via building and testing a laboratory prototype. The experimental results showed the capability of the proposed system isolating the fault within 3.6 ms, which is quite fast compared to other presented systems in the relevant literature.

An Ultralow-Loss Fault-Current-Limiting Z-Source LVDC Circuit Breaker Using Cryogenic Power Electronics

Room-temperature power electronics based DC circuit breakers and fault current limiters face two major challenges: high conduction loss, and time-delayed response. This letter presents a novel circuitry, for the first time (based on literature studies), to combine cryogenic power electronics (CPE), together with the superconducting Z-source DC circuit breaker technology. The design, fabrication and tests of the new device were carried out, and 3 advantages were proved: (1) The actual overall system loss (including cryogenic issues) reduced by 62.1% in the 2 kW case study; (2) The no-delay automatic fault current limiting technology provided a sudden protective resistor ∼0.1 Ω to suppress the fault below 200 A, and meanwhile stabilized the bus voltage; (3) The CPE-based breaker achieved both the active device isolation and passive fault isolation within 60 μs.

Research on a Secondary Active Limiting DC Fault Current Limiter Topology

The current-limiting performance of the smoothing reactor is weak. The traditional saturated core-type fault current limiter (TFCL) is better, but will cause the dc circuit breaker (DCCB) to endure high overvoltage, energy absorption and also increase the current fall time. When DCCB recloses on the permanent fault, the whole dc system will face a harmful second shock that cannot be solved effectively by TFCL. To solve the above problems, a secondary active limiting fault current limiter (SAFCL) topology is proposed. It can reduce the DCCB overvoltage and energy absorption greatly. Meanwhile, it can store fault energy and uses it to active limit the current when the DCCB recloses on the permanent fault. The secondary active current limiting effect is better than the first and the DCCB breaking electric stress is lower than the first. First of all, the topology and principle of the SAFCL are introduced. The main electromagnet parameters are then analyzed. The performance of different FCLs are simulated comparatively to verify the superiority of the SAFCL. Final, the experiment is carried out, the comparison with simulations verifies the feasibility of the SAFCL.

A Bidirectional Active DC Fault Current Limiter Based on Coupled Inductor

When a fault occurs on the dc side of the voltage source converter based high voltage direct current (VSC-HVDC) transmission system, the fault current rises quickly due to the low damping of the dc system. Using a dc fault current limiter (DC-FCL) to limit the rise of the fault current can significantly reduce the breaking requirements of the DCCB. A topology of a bidirectional active dc fault current limiter (BA-FCL) based on coupled inductor is proposed in this paper. No expensive full-controlled power electronic devices are used in this topology. Only a few half-controlled power electronic devices are used to achieve active control of the current limiting unit. Compared with many topologies of current limiter at present, the fault current limiting effect of BA-FCL is improved significantly while the cost, volume, topology complexity, and control complexity are reduced. The stress analysis and parameter design of the proposed current limiter are carried out. Finally, the simulation case study and hardware experiment are implemented to verify the good economy and current limiting performance of the proposed topology.

An Improved Submodule Topology of MMC With Fault Blocking Capability Based On Reverse-Blocking Insulated Gate Bipolar Transistor

The missing capability of DC fault current limitation is an inherent disadvantage in the typical half-bridge modular multilevel converter (MMC), which restricts its application in long-distance high voltage direct current (HVDC) systems. The full-bridge submodule (FBSM) and clamped double submodule (CDSM) topologies allow for fault current self-clearing, but also suffer from additional hardware cost and power losses. In this paper, an improved submodule topology utilizing the new reverse-blocking insulated gate bipolar transistor (RB-IGBT) is proposed to improve system economy without compromising its performance. The operating principles and DC fault characteristics of the proposed topology are analyzed in details, including comparison with various topologies in terms of cost, losses, fault current clearing speed and thermal. Compared with the traditional CDSM topology, the proposed RBSM can clear DC faults faster with reduced cost of switching devices. A DC fault protection strategy for MMC-HVDC system is also presented. Simulation results under normal operating, permanent and transient fault conditions are carried out to verify the effectiveness of the proposed topology.

A Novel I-SFCL Concept for Application in Flexible DC Grid Considering the Operation Stability

DC fault current limitation is the key technique to improve the reliability and security of flexible dc grid operation. But the traditional dc fault current limiting method, which directly installs inductor in dc grid, will seriously deteriorate transient response ability and operation stability of the dc grid. In this paper, a simple I-SFCL topology is proposed. According to the theoretical analysis, the I-SFCL has similar ability of limiting dc fault current compared with the method directly installing dc inductor. And it can effectively eliminate negative effect of dc inductor on system transient response ability and operation stability. Finally, the simulation cases based on PSCAD/EMTDC proves the correctness of theoretical analysis and superiority of the proposed I-SFCL.

DC Fault Current Analyzing, Limiting, and Clearing in DC Microgrid Clusters

A new DC fault current limiter (FCL)-based circuit breaker (CB) for DC microgrid (MG) clusters is proposed in this paper. The analytical expressions of the DC fault current of a bidirectional interlink DC/DC converter in the interconnection line of two nearby DC MGs are analyzed in detail. Meanwhile, a DC fault clearing solution (based on using a DC FCL in series with a DC circuit breaker) is proposed. This structure offers low complexity, cost, and power losses. To assess the performance of the proposed method, time-domain simulation studies are carried out on a test DC MG cluster in a MATLAB/Simulink environment. The results of the proposed analytical expressions are compared with simulation results. The obtained results verify the analytical expression of the fault current and prove the effectiveness of the proposed DC fault current limiting and clearing strategy.

Interconnected standalone DC microgrid fault protection based on Self-Adaptive DC fault current limiter with hybrid solid state circuit breaker

<abstract><p>DC system has the potential of vast and rapid fault current generation due to multiple (line and converters) discharge capacitors and small impedance of DC lines. DC fault current spreads through the system exponentially compared to AC. Such an unexpected huge current causes a voltage drop, impacts the normal operation of system components and exposes the system to a great challenge for fault detection and interruption. For prevention of system destruction during the fault, multiple approaches such as application of Mechanical Circuit Breakers (MCBs), fuses, Solid State Circuit Breaker (SSCB), and Hybrid Solid-State Circuit Breaker (HSSCB) have been proposed and applied. In DC fault applications, fast fault detection and interruption without any interference to the other components are quite important. Therefore, semiconductor breakers have been implemented to meet the DC fault protection requirements with a high-speed operation where traditional MBs have failed. Due to the high conduction loss and low efficiency of semiconductor switches, for fast and efficient DC fault interruption, different Fault Current Limiter (FCL) types are suggested. Although a high impedance FCL can prevent the voltage fluctuations due to the current decline, it can cause operation speed issues, coordination troubles, overheat, and malfunction of protective components in a fault situation.</p> <p>This paper focused on a combination of two-way HSSCB with a self-adapt DC short current limiter, ultra-fast switch, and power electronic switch to overcome the above challenges. It can efficiently and fast fault current limiting response with low conducting loss and appropriate cooperation among protective components in a low voltage DC system. The MATLAB/Simulink is used to analyze the effectiveness and consistency of the proposed FCL-HSSCB in 400 <italic>V</italic> interconnected standalone DC microgrids.</p></abstract>

A kind of DC fault current-limiter with instantaneous by-pass of current-limiting reactor

With the rapid development of DC power grids, the protection of DC power grids is particularly important. Therefore, this paper proposes a kind of DC fault current-limiter with instantaneous by-pass of current-limiting reactance, analyses its working principle and theoretical calculations, and verifies the correctness of its principle through simulation experiments. At the same time, the experimental results show that the current-limiter proposed in this paper can not only instantaneously and greatly limit the fault current when a short-circuit fault occurs in the power grid, but not affect the normal operation of the power grid. A new device is provided for DC gird fault current-limiting protection.

Topology Modeling and Design of a Novel Magnetic Coupling Fault Current Limiter for VSC DC Grids

In a voltage-source converter dc grid, a dc fault current limiter (FCL) is a key apparatus. When faults occur, it is supposed to effectively and immediately suppress transient short-circuit current to protect other equipment, e.g., converters. Additionally, it is required to bring as little negative effect as possible under normal operation. Although the respective advantages are highlighted in different FCLs, one or two key disadvantages can significantly decrease the overall performance. In this article, a novel magnetic coupling FCL (MCFCL) is proposed and achieves a good balance among its advantages and disadvantages. An MCFCL consists of a mutual inductor and some power electronic switch modules. The mutual inductor metallic primary winding is connected in series to the transmission line and magnetically coupled with the secondary winding. The secondary side impedance is controlled by the power electronic switch modules. The novel 4-segment model is proposed to demonstrate the current-limiting physics, formulate the current-limiting effect, and support the design. One medium voltage (10 kV) case study is carried out based on the numerical simulation. The MCFCL shows a better current-suppressing effect and a lower impedance under normal operation than the benchmark Reactor FCL. Finally, this article is validated on a scaled-down experimental facility.

A Resistance Model of Fault Current Limiting Coils Under DC Impact

The short-circuit fault current on the dc side affects the operation safety of the multiterminal flexible HVdc (MTDC) transmission system seriously. The resistance-type superconducting fault current limiter (RSFCL) has received extensive attention in limiting the dc impact current because it has a fast response speed and zero impedance at a steady state. At present, there are so many works on the simulations of RSFCLs but the error is relatively larger, which affects the design accuracy of RSFCLs. In this article, the characteristics of dc fault current limiters are studied. The resistance and other parameters of yttrium barium copper oxide (YBCO) samples under the dc impact are measured. The equivalent heat capacity and the equivalent heat dissipation of YBCO tapes are defined and calculated to analyze the heat transfer process of YBCO tapes under the dc impact. A modeling method based on the equivalent heat parameters is obtained. In addition, the thermal balance point during the dc impact is defined by that thermal power production and heat loss of the YBCO tape are equal to identify the credible boundary of the resistance curve. Finally, the correctness of the proposed method is verified by the experimental results of fault current limiter coils and compared with the R-Q fit model. This research aids in the simulation analysis and optimization design of dc RSFCLs.

Preface

This proceeding contains the papers presented at the 3rd Asia Conference on Energy and Electrical Engineering (ACEEE 2020), and the workshop, the 3rd International Conference on Power and Smart Grid, which was scheduled to be held in Kuala Lumpur, Malaysia on May 29-31, 2020.When initially challenged by the ACEEE 2020 Conference Committee to propose to postpone ACEEE 2020 to next year or to the end of 2020, we immediately realize that unforeseen circumstances are still on the way. After evaluating the current COVID-19 situation and referring other successful virtual conferences, ACEEE 2020 had to make the difficult decision to move to a fully virtual conference this year. We felt this to be a unique opportunity to provide a more flexible way for researchers, professionals and other experts from around the world to present their research results in Energy and Electrical Engineering.We are happy to introduce that our committee was composed of about thirty excellent experts and scholars in the field of Energy and Electrical Engineering from various famous universities around the globe. Especially, we are honored to invite five distinguished keynote speakers to perform their valuable research achievements. Prof. C. Y. Chung (IEEE Fellow), University of Saskatchewan, Canada, presented a speech entitled Efficient Uncertainty Modeling for Optimal Planning and Operation of Modern Power Systems; Prof. C. K. Michael Tse, City University of Hong Kong, China, talked about Modelling and Analysis of Cascading Failure in Power Systems; Prof. Z.Y. Dong (IEEE Fellow), University of New South Wales, Australia, held his talk on Distributed Renewable Energy Resource Uptake Methodologies; Prof. Junye Wang, Athabasca University, Canada, who shared with us his speech on Decentralized Renewable Energy in Cold Climate Regions: Challenges and Opportunities. Lastly, Prof. Zhixin Wang, Shanghai Jiaotong University, China, discussed his study on DC Fault Current Limiter and Application in VSC-HVDC Transmission System. The professional research of the five speakers stimulated in-depth communication between the participants via Zoom online rooms, and also provided new ideas for scholars in the field of energy and power, which enabled the conference a great success.

Bridge‐type fault current limiter and hybrid breaker for HVDC grids applications

The fast raising nature of DC fault currents and sensitivity of high-voltage DC (HVDC) power converters to DC faults is critical protection issues. On the other hand, DC fault current does not meet zero; which causes DC to fault current breaking process become more challenging. Specifically, to protect HVDC grids against DC fault currents, the development of very fast breakers is crucial. This study proposes a DC fault current limiter and breaker, which is able to protect the HVDC system/grid in a very fast and safe manner. The main goal of this study is to enhance the performance of already in the market hybrid DC circuit breakersincluding the magnitude of fault current and breaker operation speed. In the proposed HVDC fault current limiter and breaker, the fault current is limited in two stages by an inductive and resistive current limiter, which drastically decreases the main breaker dissipated energy. The functionality of the proposed HVDC fault current limiter and breaker is mathematically analysed, and then verified by PSCAD and Matlab/Simulink. Finally, simulation results are validated by scaled-down laboratory examinations.

Simulation Test of a DC Fault Current Limiter for Fault Ride-Through Problem of Low-Voltage DC Distribution

The low voltage direct current (LVDC) distribution networks are connected with too many kinds of loads and sources, which makes them prone to failure. Due to the small damping value in the DC lines, the fault signal propagates so fast that the impact current with the wave front of millisecond and the transient voltage pose great challenges for fault detection. Even worse, some faults with small currents are difficult to detect and the communication is out of sync, resulting in protection misoperation. These problems have severely affected the new energy utilization. In view of this, a DC fault current limiter (FCL) composed of inductance, resistance, and power electronic switch was designed in this paper. The rising speed of fault current can be decreased by the series inductance and the peak value of the fault current can be limited by series impedance, thus in this way the running time can be gained for fault detection and protection. For distributed energy access, by deducing the short circuit fault characteristic expression of LVDC distribution network, the feasibility of FCL was verified. Based on the structure of the bridge-type alternating current (AC) current limiter, the structure and parameters of the DC FCL were determined according to the fault ride-through target. Then, a low voltage ride-through strategy based on DC FCL was proposed for the bipolar short-circuit fault of LVDC distribution network. Finally, MATLAB/Simulink simulation was used to verify the rationality of the proposed FCL and its ride-through strategy.

Modeling of the DC Inductive Superconducting Fault Current Limiter

DC fault current limiter is an important device for the dc system, because the action speed of the existing selective protection cannot match the dc fault developing speed. Due to its excellent capacity on limiting dc fault rising speed, the analyses of dc inductive type superconducting fault current limiter (I-SFCL) are attracting more attention. In this paper, a modeling method for dc I-SFCL is proposed to describe its nonlinear characteristic of inductance. Firstly, the structure and working principle of the dc I-SFCL is briefly introduced, and the magnetic equivalent circuit is established according to the magnetic field distribution. Then, the relationship between dc transient current and the current-limiting inductance of dc I-SFCL is discussed. By analyzing the equivalent magnetic circuit, a mathematical I-SFCL model is proposed in Matlab based on the actual geometric and electrical parameters. Finally, under the same dc test platform, the magnetic flux density, the voltage and the current of dc I-SFCL in Matlab model are compared with that in finite element method (FEM) model. Simulation results verifies the validity and the correctness of the model.

Simulation and experiment of a new DC fault current limiter topology

With the development of high voltage direct current (HVDC) power transmission system, it is imperative to develop a practical current limiting device which can effectively protect the converter from the influence of fault current. Based on the topology of current limiter proposed in previous papers, considering the requirements of practical application conditions, an optimized topology is proposed, which consists of snubber circuit and arrester, both in simulation and experiment. In addition, the RC buffering circuit is added and the parameters are optimized to reduce the voltage impulse that the IGBT of fault current limiter would else bear. Simulation and experiment are carried out in DC system. Both simulation and experiment results can prove the effectiveness of the optimized current limiter circuit.

Self-Powered 380 V DC SiC Solid-State Circuit Breaker and Fault Current Limiter

This paper presents a new ultrafast dc solid-state circuit breaker (SSCB) that uses a silicon carbide cascode as the main switching and limiting semiconductor and an isolated photovoltaic driver to control it. The proposed topology is self-powered and fully implemented with discrete parts. The SSCB's cascode can work in three different states—fully on during nominal operation, linear mode for current limitation, and fully off to disconnect the load. The time the SSCB operates in linear mode and the maximum current limit is easily set by discrete components. Control inputs have also been included to reset the SSCB after a fault has been removed or to remotely switch it on or off . This device can be used in dc distribution avoiding deterioration due to the problems associated with electric arcs and mechanical aging of moving parts, limiting inrush currents and also minimizing conduction losses respect other kind of circuit breakers. Functional, thermal, and efficiency tests have been carried out with three different 380 V prototypes. Experimental results show the excellent behavior of the SSCB, it is able to block a 380 V short circuit failure in 570 ns; the authors have not found any faster results in the literature.