dBm Optical Modulation Amplitude Research Articles

100 Gbit/s PAM-4 Linear Burst-Mode Transimpedance Amplifier for Upstream Flexible Passive Optical Networks

Next-generation passive optical networks (PONs) with upstream rates of 50 Gbit/s and beyond will require a new class of burst-mode transimpedance amplifiers (BMTIAs) that are linear to enable (digital) equalization of channel impairments. Such linear BMTIAs also enable higher-order modulation formats like 4-level pulse amplitude modulation (PAM-4). In this paper, we demonstrate operation of a novel linear BMTIA integrated together with a commercial off-the-shelf 25G-class avalanche photodiode (APD), achieving 50 Gbit/s non-return-to-zero (NRZ) operation with a sensitivity of -23.7 dBm optical modulation amplitude (OMA) and dynamic range exceeding 21.7 dB and 100 Gbit/s PAM-4 operation with a sensitivity of -15.8 dBm OMA and dynamic range exceeding 15.4 dB, both at a bit error ratio (BER) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$10^{-2}$</tex-math></inline-formula> . In addition, fast burst-mode gain-control and balancing circuits limit loud-soft sensitivity penalties in the case of AC-coupled circuits to less than 1.3 dB. The chip was designed in a 0.13 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula> m SiGe:C BiCMOS technology, has an area of 1.2×1.7 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^{2}$</tex-math></inline-formula> and consumes between 260 mW and 310 mW. This receiver paves the way to a next-generation class of BMTIAs, supporting the ITU-T G.9804.3 Amd 1 standard.

Avalanche Photodiodes with Dual Multiplication Layers for High-Speed and Wide Dynamic Range Performances

In this work, we demonstrate In0.52Al0.48As top/backside-illuminated avalanche photodiodes (APD) with dual multiplication layers for high-speed and wide dynamic range performances. Our fabricated top-illuminated APDs, with a partially depleted p-type In0.53Ga0.47As absorber layer and thin In0.52Al0.48As dual multiplication (M-) layer (60 and 88 nm), exhibit a wide optical-to-electrical bandwidth (16 GHz) with high responsivity (2.5 A/W) under strong light illumination (around 1 mW). The measured bias dependent 3-dB O-E bandwidth was pinned at 16 GHz without any serious degradation near the saturation current output. To further increase the speed, we downscaled the active diameter and adopted a back-side illuminated structure with flip-chip bonding for batter optical alignment tolerance. A significant improvement in maximum bandwidth was demonstrated (25 versus 18 GHz). On the other hand, we adopted a thick dual M-layer (200 and 300 nm) and 2 μm absorber layer in the APD design to circumvent the problem of serious bandwidth degradation under high gain (&gt;100) and high-power operation which significantly enhanced the dynamic range. Due to dual M-layer, the carriers could be energized in the first M-layer then propagate to the second M-layer to trigger the avalanche process. In both cases, despite variation in thickness of the absorber and M-layer, the cascade avalanche process leads to values close to the ultra-high gain bandwidth product (GBP) of around 460 GHz with a responsivity of 0.4 and 1 A/W at unit gain for the thin and thick M-layer devices, respectively. We successfully achieved a good sensitivity of around −20.6 dBm optical modulation amplitude (OMA) at a data rate of 25.78 Gb/s, by packaging the fabricated APDs (thin dual M-layer (60 and 88 nm) version) with a 25 Gb/s trans-impedance amplifier in a 100 Gb/s ROSA package. The results show that, the incorporation of a dual multiplication (M) layer structure in the APD opens a new window to obtaining the higher GBP in order to meet the requirements for high-speed transmission without the need of further downscaling the multiplication layer.

Design Considerations for Energy Efficient DWDM PAM4 Transceivers Employing Avalanche Photodiodes

AbstractAn effective approach to increase per‐fiber bandwidth is to combine per‐wavelength four‐level pulse amplitude modulation (PAM4) with dense wavelength division multiplexing (DWDM). Silicon photonic transceivers based on microring resonator modulators and drop filters can allow for an efficient realization of this. Utilizing avalanche photodiodes (APDs) in the receiver front‐ends of these transceivers can significantly improve sensitivity, allowing for reduced source laser power and overall improved power efficiency. This paper analyzes the optical‐modulation amplitude (OMA) sensitivity of these APD‐based PAM4 receivers in a silicon photonic DWDM link. A comprehensive link budget is considered that takes into account various system losses and relevant noise sources. Modeling with a developed APD that has a maximum 230 GHz gain‐bandwidth product predicts sensitivity improvements at 32 to 64 Gb s−1 PAM4 ranging from 9.8 to 12 dB relative to a conventional p‐i‐n photodiode. Scaling the APD gain‐bandwidth to 310 GHz allows support of 112 Gb s−1 with −13.2 dBm OMA sensitivity at a BER of with an APD gain of 10. Utilizing the presented architecture, link budget analysis predicts a 9.5x reduction in laser power with APDs and that 38 mW source laser optical power can support a four‐channel DWDM link operating at an aggregate 448 Gb s−1 data rate.

A Compact Integrated Receiver Optical Sub-Assembly With High Sensitivity and Low Crosstalk for 100 Gb/s Ethernet Systems

A 25Gb/s guardring-free planar AlInAs avalanche photodiode (APD) and 100-Gb/s APD receiver optical sub-assembly (ROSA) employing a quasi-collimated beam for reducing the optical loss and optical demultiplexer (DEMUX) size are demonstrated for a 40-km optical link. The APD so fabricated achieves a very low dark current of 63 nA at a multiplication factor of 10, with a high gain-bandwidth product of 225 GHz due to the optimum multiplication layer and absorption layer. Additionally, the assembled APD ROSA exhibits a high receiver sensitivity of more than −23 dBm optical modulation amplitude (OMA) (BER = 5.0 × 10−5) at temperatures ranging from −5 to 80 °C for each lane. Investigating the transmission over fibers with dispersions of −119 and +40 ps/nm reveals that a sufficiently low penalty of less than 0.9 dB is obtained for all lanes. Furthermore, it is confirmed that the APD ROSA suffers little crosstalk penalty thanks to the isolation achieved by this design of optical DEMUX.

A 26-Gb/s 3-D-Integrated Silicon Photonic Receiver in BiCMOS-55 nm and PIC25G With −15.2-dBm OMA Sensitivity

This letter presents a 3-D-integrated 26 Gb/s opto-electrical receiver front-end. The electronic integrated circuit (EIC) is fabricated in a BiCMOS-55-nm technology, flipped and placed on top of the photonic integrated circuits (PICs) die through copper pillars. In the receiver chain, a fully differential shunt-feedback TI amplifier (FD-SF TIA) is followed by a limiting amplifiers (LAs) with embedded equalization, output driver and an automatic offset cancelation loop. The whole receiver provides a transimpedance (TI) gain of 76 dBΩ with 30-GHz bandwidth. By exploiting the FD-SF TIA with low parasitic capacitance of the Germanium dual heterojunction photo diode (Ge-PD) in the photonic die, the receiver achieves sensitivity of -15.2 dBm optical modulation amplitude (OMA) at Ge-PD and -10-dBm OMA at the single-mode fiber (SMF) optical output with bit error rate of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> and PRBS 15. The sensitivity is aligned with state-of-the-art receivers employing discrete photonics and, to author's best knowledge, it is the lowest reported among published 25 Gb/s receivers exploiting silicon photonics.

High-Speed In0.52Al0.48As Based Avalanche Photodiode With Top-Illuminated Design for 100 Gb/s ER-4 System

High-speed top-illuminated avalanche photodiodes (APDs) with large diameters (25 μ m) are demonstrated for the application of 4-channels 100 Gb/s data rate. They achieve a bandwidth of 17 GHz at low-gain (MG = 6.2; 3.6 A/W) and large-gain bandwidth (responsivity bandwidth) product (410 GHz (237.8 GHz-A/W); 55% external efficiency at the unit gain) while maintaining invariant high speed (14 GHz) under high power (0.5 mW) and 0.9 Vbr operations. By packaging the demonstrated APD with a 25 Gb/s transimpedance amplifier in a 100 Gb/s ROSA package, a good sensitivity of around –20.6 dBm optical modulation amplitude (OMA) at the data rate of 25.78 Gb/s has been successfully demonstrated. The achieved sensitivity not only meets the required receiver sensitivity (–18.5 dBm OMA) in 100 GbE-ER-4 Lite (40 km) system, it is also comparable with that of the high-performance 100 Gb/s ROSA incorporated with the back-side illuminated APD design. Overall, our novel APD structure can eliminate the costly flip-chip bonding package in the 100 Gb/s ROSA without sacrificing its sensitivity performance.

A 50-Gb/s High-Sensitivity (−9.2 dBm) Low-Power (7.9 pJ/bit) Optical Receiver Based on 0.18-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\mu$ &lt;/tex-math&gt; &lt;/inline-formula&gt;m SiGe BiCMOS Technology

A 50-Gb/s optical receiver (RX) based on 0.18- $\mu \text{m}$ SiGe BiCMOS technology was fabricated and evaluated. To improve the horizontal eye opening and sensitivity of the RX without degrading its power efficiency, it is configured with a two-stage pre-amplifier with high gain (56 dB $\Omega $ ) and high bandwidth (35 GHz), a high-accuracy automatic decision-threshold control (ATC) consisting of power-supply variation and offset cancellers for improving sensitivity, and a jitter-reduction packaging structure for improving transimpedance flatness. The RX achieves high sensitivity of −9.2 dBm, while its power consumption is 7.9 pJ/bit at a data rate of 50 Gb/s. In 50- and 56-Gb/s transmission tests through a 100-m multi-mode fiber (MMF), it demonstrated error-free operation at the bit error rate (BER) of less than 10–12 with the sensitivities of −9 and −6.1 dBm optical modulation amplitude (OMA). It also demonstrated 300-m error-free MMF transmission (at 50 Gb/s) with the practical sensitivity of −7.6 dBm OMA.

40-Gbit/s 850-nm VCSEL-Based Full-CMOS Optical Link With Power-Data Rate Adaptivity

An optical link based on directly modulated vertical-cavity surface-emitting laser (VCSEL) at 850-nm wavelength using commercial VCSEL and photodiode operating error-free BER < 10−12) at 40 Gbit/s is reported. The transmitter is implemented in a 14-nm FinFET CMOS while the receiver (RX) in 28-nm digital bulk-CMOS technologies. This is the fastest 850-nm VCSEL-based single-lane non-return-to-zero optical link with all the analog front-end components fabricated in CMOS. An energy-per-bit of 3.4 pJ/bit is measured at 40 Gbit/s. At lower data rates, the bandwidths of the circuits can be decreased adaptively to save power. This results in 2.7 pJ/bit at 20 Gbit/s. A sensitivity of −1.9 dBm optical modulation amplitude could be measured at the RX for 40 Gbit/s.

A 32 Gb/s, 4.7 pJ/bit Optical Link With −11.7 dBm Sensitivity in 14-nm FinFET CMOS

This paper presents a 32 Gb/s non-return-to-zero optical link using 850-nm vertical-cavity surface-emitting laser-based multi-mode optics with 14-nm bulk FinFET CMOS circuits. The target application is the integration of optics on to the first-level package, connecting high-speed optical I/O directly to an advanced CMOS host chip (e.g., processor and switch) to increase package I/O bandwidth density and lower overall system power and cost. The optical link is designed for maximum link margin to tolerate high optical losses created by low-cost optical packaging. The transmitter (TX) uses a three-tap, 1/2-unit-interval-spaced feed-forward equalizer to improve eye opening. The receiver (RX) uses a low-bandwidth, low-noise transimpedance amplifier and a speculative one-tap decision-feedback equalizer for high sensitivity. The TX and RX power efficiencies are 3.3 and 1.4 pJ/bit, respectively. The TX optical modulation amplitude (OMA) is 1.2 dBm, and the RX sensitivity is −11.7 dBm OMA at a bit error rate of 10−12 with PRBS31 data, providing 12.9-dB link margin.

Capacitively-Coupled CMOS VCSEL Driver Circuits

A capacitively-coupled laser diode driver (LDD) for common-cathode vertical-cavity surface-emitting lasers (VCSELs) designed in 65 nm CMOS intended for short-reach parallel optical interconnects is presented. The LDD consists of a capacitively-coupled voltage-mode high-frequency path and a direct-coupled path that provides low-frequency signal components. By increasing the low-frequency path bandwidth an order of magnitude compared to previous capacitively-coupled drivers, the on-chip coupling capacitor is reduced to 1.05 pF, occupying 3 times less area than prior art. The driver incorporates capacitively-coupled two-tap pre-emphasis to equalize the VCSEL’s optical response. The VCSEL was modulated with an optical modulation amplitude (OMA) of up to +5.1 dBm and an extinction ratio of 9 dB at 15 Gb/s, the highest extinction ratio achieved in high-speed anode-driving CMOS LDDs. The driver is programmable and is also demonstrated with +2.3 dBm OMA at a power consumption of only 30 mW, corresponding to an energy efficiency of 2 pJ/bit.