dB Output Power Back-off Research Articles

23.5–27.5 GHz Band Doherty Power Amplifier Integrated Circuit Using 28 nm Bulk CMOS Process Based on Dynamic Power Dividing Network

This paper presents a Doherty power amplifier (DPA) integrated circuit (IC) designed to have enhanced gain, efficiency, and AM-AM characteristics through a dynamic power dividing technique, which can control the power dividing ratio according to the input power. Since this multi-purpose dynamic power dividing network also provides the phase offset and impedance matching at the interstage network needed for appropriate DPA operation, the active IC area could be reduced. To verify the proposed technique and its analysis, the DPA was implemented with a 28 nm bulk CMOS process for the fifth-generation (5G) new radio (NR) millimeter-wave frequency band of 23.5–27.5 GHz. The measured results showed a gain of 20.3–21.9 dB, saturated output power of 14.0–15.2 dBm, power added efficiency (PAE) of 22.8–26.7% at the peak power, and PAE of 14.6–17.6% at the 6 dB output power back-off (OBO).

A Broadband Three-Way Series Doherty Power Amplifier with Deep Power Back-Off Efficiency Enhancement for 5G Application

This article presents a new broadband three-way series Doherty power amplifier (DPA) topology, which enables a broadband output power back-off (OBO) efficiency enhancement of up to 10 dB or higher. The proposed DPA topology achieves Doherty load modulation and three-way power combining through a transformer, which requires only a low coupling factor, thus facilitating its implementation in double-sided PCBs or monolithic microwave integrated circuit (MMIC) processes. The design equations for the proposed DPA topology are proposed and analyzed in detail. A proof-of-concept PA at the 2.1–2.8 GHz band using commercial GaN transistors was designed and fabricated to validate the proposed concept. Within the operating frequency band, it achieves a saturated output power (Psat) of 44.5–46.5 dBm with a peak drain efficiency (DE) of 60–72%, and 43–52% DE at 10 dB OBO. Moreover, under a 20 MHz long-term evolution (LTE)-modulated signal, the PA demonstrates a 36.8–37.5 dBm average output power (Pavg) and 47–53% average drain efficiency (DEavg). Notably, the adjacent channel leakage ratio (ACLR) is as low as −35–−28.2 dBc without any digital predistortion (DPD).

Analysis and design of broadband Doherty power amplifier using parameterized load modulation network and complex combining load

This paper presents a novel approach to design broadband Doherty power amplifiers (DPAs) with extended fractional bandwidth (FBW). A parameterized load modulation network (LMN) and complex combining loads are proposed that can extend the FBW while providing more accurate back-off impedance. To examine the influence of parameter variations in the LMN on the broadband performance of the DPA, we utilize the parameter scanning method and subsequently select the optimal parameters in the LMN. Additionally, three-dimensional computer visualization techniques is invoked to visually examine the impedance solution space of the complex combining loads. A DPA prototype with a bandwidth of 0.85–1.8 GHz is then designed and implemented using commercial GaN transistors to validate the proposed architecture. The fabricated DPA attains a measured gain of 14.2–15.7 dB and a saturated power of 43.0–44.9 dBm. Across the designed operation band, the measured drain efficiency reached 51.6%–73.6% at saturation and 43.7%–56.7% at 6 dB output power back-off. When driven by a 20 MHz modulated signal with a peak-to-average power ratio (PAPR) of 8 dB, the average efficiency of the fabricated DPA is higher than 46.7%.

A circuit solving method for output matching network parameters of Doherty power amplifiers

In this paper, all possible numerical solutions are provided when the matching conditions for Doherty power amplifier (DPA) back-off and saturation states are met. Firstly, this article presents an impedance expression of the DPA. Then all circuit parameter solutions can be solved for the load modulation of DPA using this expression. In the process of solving circuit parameters, the impedance matching of the DPA at the saturation level is established through the analysis of the S-parameter matrix. Then by limiting the impedance solution range of DPA at the output power back-off (OBO) level, the circuit parameter solutions that satisfy the specified conditions are meticulously screened. The output matching network of the DPA is designed according to the obtained circuit parameter solutions for broadband operation. To validate the proposed design method, a broadband DPA operating from 1.2 to 2.4 GHz is designed and measured based on the proposed method. Under the continuous wave excitation, the measured drain efficiency at 6 dB OBO level and saturation (SAT) level are 44%–56% and 51%-65.4% from 1.2 to 2.2 GHz, respectively. The peak output power is 45.1–46.3 dBm.

Design of a Dual-Band Load-Modulated Sequential Amplifier with Extended Back-off

This letter presents a dual-band load-modulated sequential amplifier (LMSA). The proposed amplifier changed the attenuator terminated at the isolation port of the four-port combiner of the traditional sequential power amplifier (SPA) architecture into a reactance modulation network (RMN) for load modulation. The impedance can be maintained pure resistance by designing RMN, thus realizing high efficiency and a good portion of the output power in the multiple bands. Compared to the dual-band Doherty power amplifier with a complex dual-band load modulation network (LMN), the proposed LMSA has advantages as maintaining high output power back-off (OBO) efficiency, wide bandwidth and simple construction. A 10-watt dual-band LMSA is simulated and measured in 1.7-1.9 GHz and 2.4-2.6 GHz with saturated efficiencies 61.2-69.9% and 54.4-70.8%, respectively. The corresponding 9 dB OBO efficiency is 46.5-57.1% and 46.4-54.4%, respectively.

A Ka-Band Doherty Power Amplifier in a 150 nm GaN-on-SiC Technology for 5G Applications

This paper presents a Ka-band three-stage power amplifier for 5G communications, which has been implemented in a 150 nm GaN-on-SiC technology and adopts a Doherty architecture. The amplifier is made up of a 50 Ω input buffer, which drives a power splitter, thanks to which it delivers its output power to the two power amplifier units of the Doherty topology, namely the main and auxiliary amplifier. Finally, the outputs of the two power amplifiers are properly arranged in a current combining scheme that enables the typical load modulation of the Doherty architecture, alongside allowing power combining at the final output. The proposed amplifier achieves a small signal gain of around 30 dB at 27 GHz, while providing a saturated output power of 32 dBm, with a power-added efficiency (PAE) as high as 26% and 18% at peak and 6 dB output power back-off, respectively.

Application of Load-Pull X-Parameters for GaN Device-Based Load Modulated Balanced Power Amplifier Design

In this work, the design of a load modulated balanced power amplifier (LMBA), which composed of a pair of classical balanced power amplifier (BA) and a signal control power amplifier (CA), based on using the X-parameter model is presented for the first time. A 10-W gallium nitride (GaN) packaged transistor is used for the power amplifier (PA) design. The extracted X-parameter model of the device under test (DUT) can accurately predict the nonlinear behavioral of the device, including both fundamental and harmonic characteristics, and determine the region of the Smith chart that leads to the optimal output power and drain efficiency (DE), with which the BA and CA are designed. In order to facilitate the application of the X-parameter for LMBA design, the X-parameter model of the classical BA pair is further extracted. Finally, an LMBA is fabricated and tested to verify the validity of the proposed design methodology. The measurements performed on the developed prototype show a saturation output power of up to 43.2 dBm in the frequency range of 1.3 GHz-1.6 GHz, with a saturation DE over 73% and an output power back-off (OBO) efficiency over 51% when it has more than 9 dB output power back-off. A single-carrier 20-MHz long-term evolution (LTE) signal is used to test the designed PA, and performance of the amplifier both with and without linearization are given.

A Dual Load-Modulated Doherty Power Amplifier Design Method for Improving Power Back-Off Efficiency.

In this paper, the load modulation process of a Doherty power amplifier (DPA) is analyzed to address the issue of why designed DPAs have a very low efficiency in the back-off state in some cases. A general formula of the real load modulation process is also given for analyzing the load modulation of a peak PA matching network. This provides a new perspective for improving the back-off efficiency of a DPA. To improve the power back-off efficiency of a DPA, a dual load-modulated DPA (D-DPA) design method is proposed. The core principle of the proposed design method is to control the load modulation process from the carrier PA to the peaking PA based on the design method of the traditional two-way DPA. The efficiency of the peaking PA in the back-off region is enhanced, thereby improving the efficiency in the entire back-off region of the DPA. Based on the proposed design method, a D-DPA operating at 2 GHz is designed and fabricated. The test results show that the saturated output power and gain are 43.7 dBm and 9.7 dB, respectively, while the efficiency at 6 dB output power back-off is 59.2%. The designed D-DPA eliminates the efficiency pit of the traditional two-way DPA in the output power back-off region.

TCAD assisted design of the Doherty Power Amplifier

Nonlinear physics-based TCAD simulations based on the Harmonic Balance technique represent an important tool to link the performance of microwave circuits to the active device fabrication technology (Donati Guerrieri et al., 2016 [1,2]). While nonlinear TCAD simulations were previously limited to the analysis of circuits including a single device, starting from Donati Guerrieri et al. (2022) they have been extended to circuits with multiple interacting devices. This work, further extending Donati Guerrieri et al. (2022), shows a complete example of the design of a Doherty Power Amplifier fully assisted by TCAD nonlinear simulations. The analysis allows for a complete inspection of the internal physical variables of the DPA, including carrier concentrations and electrostatic potential, making it possible to verify the correct operation of the main and auxiliary devices. The proposed DPA, exploiting a GaAs MESFET technology, achieves 30 dBm output power at 12 GHz with peak Power Added Efficiency (PAE) of 52% at 6 dB Output Power Back-off (OBO) and 5 dB gain. The reported results show that the power split ratio between the MAIN and AUX amplifier can be used to achieve a good compromise between linearity and efficiency.

Analysis of Doherty Power Amplifier Matching Assisted by Physics-Based Device Modelling

The Doherty Power Amplifier represents one of the most promising solutions for the design of high-efficiency power stages. In the widely adopted ABC scheme, the Doherty Amplifier design critically depends on the accuracy of the device model in different operating conditions, ranging from class AB to class C. For the class C case, library models are often inaccurate, while experimental characterization is difficult since it must be carried out in large signal conditions and with varying gate bias. In this paper, we propose an alternative approach, based on physics-based Technological CAD (TCAD) simulations of the complete Doherty amplifier along with the analysis of its individual MAIN (class AB) and AUXILIARY (class C) stages. TCAD simulations seamlessly provide an accurate modelling of the device behavior in all operation classes, including the device turn-on and the nonlinear capacitances, and easily account for the cross-loading effects of the MAIN and AUXILIARY devices through the output network and the effect of the device feedback (gate-drain) capacitance on the input matching. Analyzing a GaAs Doherty stage at 12 GHz, we show that the input phase of the auxiliary stage can be exploited for the Doherty power amplifier optimization in terms of gain, linearity and efficiency, showing a 9 dB gain with less than 1 dB gain variation from back-off to peak power with a power-added efficiency exceeding 45% over a Doherty region extending to a more than 6 dB output power back-off.

A Broadband Analog Predistortion Linearizer Based on GaAs MMIC for Ka-Band TWTAs

In this article, a Ka-band broadband analog predistortion (APD) microwave monolithic integrated circuit (MMIC) with independent tunability based on a 0.15 μm GaAs pHEMT process is proposed, which can be cascaded in front of traveling wave tube amplifiers (TWTAs) to improve their linearity. The influence of different diode sizes on the parameters of Schottky diodes is analyzed and used to design the gain and phase nonlinear branches. The broadband APD MMIC is realized based on a dual-branch vector synthesis design and nonlinear frequency adjust module (NFAM). The independent tunability and broadband characteristics of the APD MMIC are verified by simulated and measured results with an error of less than 5%. Furthermore, a Ka-band 60 W TWTA is linearized by the APD MMIC, and the gain and phase compressions are reduced from 8 dB and 50° to within 3 dB and 12°, respectively. The third-order intermodulation (C/IM3) is greater than 28 dBc and noise power ratio (NPR) is greater than 15.7 dBc at 3 dB output power backoff (OPBO) over the operating band of 25.1~27.5 GHz, indicating that the APD MMIC can improve the nonlinearity of TWTA effectively under broadband signals.

Design of a broadband Doherty power amplifier with a modified load modulation network

This article proposes a modified load modulation network (LMN) to adjust the structure of the traditional Doherty power amplifier (DPA) by changing one λ/4 microstrip line at the output of the main power amplifier into two in the traditional DPA and connecting a terminal open-circuit λ/2 line at the junction point which can reduce the frequency dispersion effect to achieve expanding bandwidth while maintaining saturation efficiency and back-off efficiency. A 2.6–3.6 GHz DPA is designed and fabricated for verification. The measured results show that the saturated output power is 42.5–44 dBm and the saturated efficiency is between 63% and 69% in target band with a gain from 8.5 to 9.5 dB. At 6 dB output power back-off, the drain efficiency is 44%–50%. And the adjacent channel power ratio (ACPR) is better than −32 dBc.

A novel compact asymmetric Doherty PA design using symmetric transistors

AbstractA novel 7.2 dB output power back off Doherty power amplifier (DPA) based on asymmetrical load is proposed using two same transistors in this paper. To get maximum efficiency at back‐off output power and the largest saturate output power level simultaneously, the carrier power amplifier (PA) is matched to the maximum efficiency region when peaking PA is almost off, and both of the two PAs are matched to maximum power region to get largest output power. According to the proposed design methodology, high efficiency at back‐off power and high peak power DPA is designed and fabricated with two Cree's GaN HEMT CGH40010F devices. Measurements results show that the saturated output power of the DPA is over 44.5 dBm, the drain efficiency when 7.2 dB output power back off and saturate power are above 42% and 53%, respectively, in the range of 3.4–3.8 GHz. Meanwhile, better than −47.8 dBc adjacent channel leak power ratio can be achieved with digital predistortion under 20 MHz LTE signal testing at 3.4 GHz, the final design size is only 14 × 12 cm2.

High efficiency Doherty power amplifier based on asymmetrical matching network

Doherty power amplifier (DPA) with high efficiency at the output power back off is highly demanded for modern wireless communication systems to achieve high data rates and reduce the power consumption and operation costs. This paper presents a new design strategy for enhancing DPA’s back-off efficiency. New design strategy called asymmetrical matching network is used to achieve asymmetric operation, which helps to compensate for the low power delivered by the peaking stage in the conventional DPA. The simulation results showed an enhancement in the back-off efficiency, where the proposed design is able toachieve 46-52% drain efficiency at 8 dB output power back-off while maintains high efficiency of 73-80 % at saturation over the designed bandwidth of 3.4-3.6 GHz. The proposed design is suitable for high efficiency sub-6 GHz fifth-generation wireless applications.<br /><div> </div>

Theory and Design Methodology for Reverse-Modulated Dual-Branch Power Amplifiers Applied to a 4G/5G Broadband GaN MMIC PA Design

This article presents a generalized theory and new design methodology for reverse-load-modulated dual-branch (RMDB) power amplifiers (PAs), which uses a current-biased transistor in the main branch to realize optimal load modulation without using the impedance transformers at the output of the PAs. Consequently, this topology offers a proper load modulation mechanism over a wider frequency bandwidth. Besides, smaller output matching network (OMN) footprint and lower loss are suitable features for monolithic microwave integrated circuit (MMIC) designs. The proposed theory can be applied for symmetrical and asymmetrical designs to realize different output power back-off (OPBO) ranges. The theory and design methodology were used to design the first MMIC RMDB PA. The broad bandwidth of this design (2.6-3.8 GHz) allows it to cover multiple bands in 4th-generation (4G) Long Term Evolution (LTE) and 5th-generation (5G) New Radio (NR) standards. Under continuous wave (CW) excitation, the experimental results show a drain efficiency (DE) higher than 58% at peak output power (POP) and 37% at 9 dB OPBO, over the whole frequency band.

Design of a Wideband Doherty Power Amplifier with High Efficiency for 5G Application

This paper discusses the design of a wideband class AB-C Doherty power amplifier suitable for 5G applications. Theoretical analysis of the output matching network is presented, focusing on the impact of the non-ideally infinite output impedance of the auxiliary amplifier in back off, due to the device’s parasitic elements. By properly accounting for this effect, the designed output matching network was able to follow the desired impedance trajectories across the 2.8 GHz to 3.6 GHz range (fractional bandwidth = 25%), with a good trade-off between efficiency and bandwidth. The Doherty power amplifier was designed with two 10 W packaged GaN HEMTs. The measurement results showed that it provided 43 dBm to 44.2 dBm saturated output power and 8 dB to 13.5 dB linear power gain over the entire band. The achieved drain efficiency was between 62% and 76.5% at saturation and between 44% and 56% at 6 dB of output power back-off.

A 24-29.5 GHz Voltage-Combined Doherty Power Amplifier Based on Compact Low-Loss Combiner

In this brief, a 24-29.5 GHz millimeter-wave (mm-wave) voltage-combined Doherty power amplifier (DPA) based on compact low-loss combiner is proposed for the fifth-generation (5G) applications. By maximizing the use of parasitic parameters in the circuit, a compact low-loss combiner is proposed to achieve the required impedance transformation with only one additional series capacitor. A detailed design procedure is also introduced in the brief. Based on the proposed combiner, a fully integrated Doherty PA is implemented in 0.13- μm SiGe BiCMOS process with a core area of only 0.29 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The DPA achieves a 27% -3-dB small-signal gain fractional bandwidth and a 15.9 dB small signal gain at the center frequency of 27 GHz. The -1-dB Psat bandwidth covers 24-29.5 GHz (20% fractional bandwidth), and the maximum output power is 20.8 dBm ± 0.4 dB. From 24 to 29.5 GHz, the designed DPA provides 23.2% to 28.4% power-added efficiency (PAE) at saturated output power, and 18.3% to 21.9% PAE at 6 dB of output power back-off (OPBO).

Bandwidth Extension of Three-Way Doherty Power Amplifier With Reactance Compensation Using Parallel Peaking Amplifiers

This paper presents a new methodology for designing a broadband three-way Doherty power amplifier (DPA), which utilizes a reactance compensation generated by parallel peaking amplifiers to extend the bandwidth and improve the back-off efficiency. By analyzing the load impedance and efficiency of the reactance-compensated DPA, the optimal reactance at the output of the peaking amplifier required for bandwidth extension can be obtained. Then, a structure using two parallel peaking amplifiers is proposed to reduce the output reactance for the desired distribution. Using a $\lambda _{0}$ /4 transmission line, a sufficiently large output reactance of the peaking branch can be realized at the combining point over a wider frequency band, which can compensate the effective load impedance of the carrier amplifier and improve its efficiency and bandwidth. A wideband three-way DPA is designed and fabricated to verify the proposed method. Measurement results indicate that an efficiency of 50–53% at 10 dB output power back-off and a saturated efficiency of 54–68% can be achieved over the frequency range from 1.6 to 2.7 GHz.

Bandwidth Enhancement of Doherty Power Amplifier Using Modified Load Modulation Network

A novel Doherty power amplifier (DPA) architecture with extended bandwidth is presented in this paper. A modified load modulation network is introduced to provide impedance condition required by the Doherty operation in a wide frequency range. Analytical parameter solutions of the proposed load modulation network and the related load modulation process are presented. A DPA with 2.80-3.55 GHz bandwidth utilizing commercial GaN transistors is implemented. The fabricated DPA attains a measured 9.3-11.1 gain and 43.0-45.0 dBm saturated power. 50.0-60.6% and 66-78% drain efficiency is obtained at 6 dB output power back-off and saturation throughout the designed band, respectively. Moreover, the back-off drain efficiencies are higher than 55% within 700 MHz bandwidth. When driven by a 6-carrier 120 MHz OFDM signal with 7.0 dB peak to average power ratio, the proposed DPA achieves adjacent channel leakage ratio of better than −50 dBc after digital pre-distortion (DPD) at 3.20 GHz with average efficiency of 53.3%.

A New Design Methodology for Wideband Analog Predistorter With the Characteristics of Frequency-Dependent Gain and Phase Conversions

A novel design method, which can transform the nonlinear circuits design to the impedance matching network (IMN) design, is proposed for wideband analog predistoter (APD) with the characteristics of frequency-dependent gain and phase conversions in this paper. First, the design method for the desired gain and phase conversions is introduced. The ABCD parameters of the IMN can be computed. To simplify the design, the obtained parameters are transformed to the IMN terminal impedance. Then we can only need to design the IMN terminal impedance to obtain the desired transfer characteristics. In the meanwhile, an APD with 4.5 dB gain conversion and 50° phase conversion is designed and simulated to validate the design method for specify gain and phase conversions. The simulated results show good effectiveness of the design method. Second, for wideband application, the complex gain and phase conversions surface design is transformed to the IMN terminal impendence curve versus frequency design. This gives the designers a well-defined strategy for wideband APD design focusing on frequency-dependent phase conversion as well as gain conversion. To validate the proposed method, a wideband APD operating at K-band (17-20 GHz) is designed, fabricated and measured. A linearized 100W K-band TWTA is shown to achieve a noise power ratio (NPR) >20 dB at 3 dB output power back-off, and phase change <; 6.5° among the operating band.