dB NF Research Articles

A 1–6 GHz Reconfigurable Low-IF Harmonic Mixing Receiver with 2.2–2.6 dB NF and 33–38 dB IMRR in 65 nm CMOS for Wireless Applications

A 1–6 GHz Reconfigurable Low-IF Harmonic Mixing Receiver with 2.2–2.6 dB NF and 33–38 dB IMRR in 65 nm CMOS for Wireless Applications

A reconfigurable RF front-end for 5G direct sampling receivers with an optimized calibration scheme

This paper presents a reconfigurable radio frequency front-end (RFFE) tailored for direct RF sampling receivers operating within Frequency Range 1 (FR-1) of the 5G spectrum. It consists of a balun-LNA, a noise-cancelling, current-reuse, Q-enhanced filter, and a programmable gain amplifier (PGA). Fabricated in 22-nm FD-SOI technology, the RFFE covers the entire frequency range from 1.7 to 6.4 GHz with a tunable bandwidth ranging from 50 MHz to 1.2 GHz. The experimental results confirm that the RFFE achieves 3.9 dB NF, 55 dB ultimate OOB rejection, −4 dBm IB-IIP3, and 23 dBm OOB-IIP3. Furthermore, a digital calibration scheme is proposed to compensate for process, voltage, and temperature (PVT) variations, achieving lower than 2 % error in 6.61 µs on average. Subsequently, a proximal policy optimization (PPO) agent is employed to choose the optimal policy for the successive adjustments of quality factors and resonance frequencies of the filter’s resonators. As a result, the proposed reinforcement learning algorithm reduces the calibration’s convergence time by 59 %.

A 0.65 V 4 dB NF 2.4 GHz Sub-Passive RF Down-Converter With Trans-Frequency Current-Reusing Scheme Achieving Low Flicker Noise and High Linearity

A 0.65 V 4 dB NF 2.4 GHz Sub-Passive RF Down-Converter With Trans-Frequency Current-Reusing Scheme Achieving Low Flicker Noise and High Linearity

A 4–22 GHz Ultra-Wideband Low-Noise Amplifier With 0.8–1.5 dB NF and 28–31 dB Gain Enhanced by the Negative Load Impedance

A 4–22 GHz Ultra-Wideband Low-Noise Amplifier With 0.8–1.5 dB NF and 28–31 dB Gain Enhanced by the Negative Load Impedance

A 23.6–46.5 GHz LNA with 3 dB NF and 24 dB Gain Tuning Range in 28-nm CMOS Technology

A 23.6–46.5 GHz LNA with 3 dB NF and 24 dB Gain Tuning Range in 28-nm CMOS Technology

Radiation-resistant cerium co-doped erbium-doped fibers for C- and L-band amplifiers in a high-dose gamma-radiation environment.

We experimentally demonstrate a comparative study on the radiation-resistant cerium (Ce) co-doped erbium-doped fiber amplifiers (EDFAs) exposed to a high-dose gamma-radiation environment of 1.8 kGy/h dose rate in the C and L bands. Our results show that Ce is an effective co-dopant in the aluminosilicate EDFs for suppressing radiation-induced attenuation (RIA) of more than an order of magnitude lower than the Ce-free EDF. After exposure to a high-dose gamma-radiation of up to 10 kGy, the Ce co-doped EDF still exhibits good radiation tolerance, providing 41.6 ± 2.9 dB gain and 5 ± 0.8 dB NF from 1535-1560 nm for a -25 dBm input signal. In the L-band, we report, for the first time, the radiation-resistant EDFA with the radiation-induced gain degradation (RIGD) of 3.7 dB under 2.5 kGy irradiation and 4.4 dB under 10 kGy irradiation at 1600 nm. Also, the radiation-dependent gain coefficient and gain saturation were studied in the C and L bands. A comparison of different Ce co-doped EDFs exposed to different total gamma doses reveals the radiation impact on the amplifier performance, indicating the feasibility of using Ce co-doped EDFs for space-based optical communications, requiring robust radiation stability.

A 35mW, 2.32dB NF, 1.1° Phase Error, 18-21.2GHz Beamforming Receiver IC for Satcom on the Move (SOTM) Phased Arrays

A 35mW, 2.32dB NF, 1.1° Phase Error, 18-21.2GHz Beamforming Receiver IC for Satcom on the Move (SOTM) Phased Arrays

A Ku-band LNA with 39.2 dB gain, 1.4 dB NF and shunt inductor-based matching network

A low-noise amplifier (LNA) with minimum noise figure, improved gain, operating at Ku-band, and designed using 0.13 μm bipolar complementary metal oxide semiconductor(BiCMOS) technology is described in this article. BJT along with a matching network comprising of a shunt inductor is used for optimizing noise/impedance matching in the proposed common emitter (CE) LNA with inductive emitter degeneration. Thereby, achieving ultra-low NF and gain performance along with inbuilt ESD protection circuitry. Also, the detailed mathematical analysis of design steps, impact of impedance matching network on gain and NF performance of conventional and proposed CE LNA with inductive emitter degeneration are elaborated. This proposed LNA has demonstrated a maximum gain of 39.2 dB, almost static NF of 1.4 dB to 1.64 dB across a frequency bandwidth of 2 GHz from 15.2 GHz to 17.2 GHz. It has also demonstrated a figure-of-merit (FoM) of 18.42, IP 1dB of −29.7 dBm at 16 GHz, a power intake of 24.2 mW, and layout space of 0.468 mm2.

Collaborative gain and noise optimization: a design of 150–173-GHz cascode LNA with 22.3 dB gain and 6.92 dB NF based on the gain-noise plane

Collaborative gain and noise optimization: a design of 150–173-GHz cascode LNA with 22.3 dB gain and 6.92 dB NF based on the gain-noise plane

A 6–12 GHz Wideband Low-Noise Amplifier With 0.8–1.5 dB NF and ±0.75 dB Ripple Enabled by the Capacitor Assisting Triple-Winding Transformer

This paper presents a wideband 6-12GHz two-stage low noise amplifier (LNA) that utilizes capacitor assisting triple-winding transformer in the inter-stage matching network. The electric coupling introduced by the assisting capacitor expands the design space by allowing independent control of each effective coupling strength of the three coupled inductors. The equivalent negative resistor enhanced by this capacitor improves the quality factor of the inter-stage network at high frequencies, which further improves the overall design trade-off among gain, bandwidth and noise figure. Fabricated in a 130nm SOI CMOS process, the LNA achieves a remarkable 0.8-1.5dB NF, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt;$</tex-math> </inline-formula> -14dB S11, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt;$</tex-math> </inline-formula> -8dB S22, -11.8dBm IP <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\bf {1dB}}$</tex-math> </inline-formula> and 21.8-23.3dB power gain across the 6-12GHz passband with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm$</tex-math> </inline-formula> 0.75dB ripple while drawing 20mA from a 3.3V supply.

A 28 GHz Phased-Array Transceiver for 5G Applications in 22 nm FD-SOI CMOS.

This paper presents the design and implementation of a 28 GHz phased array transceiver for 5G applications using 22 nm FD-SOI CMOS technology. The transceiver consists of a four-channel phased array receiver and transmitter, which employs phase shifting based on coarse and fine controls. The transceiver employs a zero-IF architecture, which is suitable for small footprints and low power requirements. The receiver achieves a 3.5 dB NF with a 1 dB compression point of -21 dBm and a gain of 13 dB.

A Reconfigurable RF Filter With 1%–40% Fractional Bandwidth for 5G FR1 Receivers

This paper presents a radio frequency front-end (RFFE) for 5G New Radio (NR) receivers operating in Frequency Range 1 (FR1). The core of this RFFE is a synthetic fourth-order Q-enhanced RF filter employing gm-boosting, noise-cancelling, capacitive cross-coupling, and forward body-biasing techniques to achieve 1.7 GHz to 6.4 GHz operating range and 1 adjustable fractional bandwidth (FBW). The function of the filter is based on subtracting out-of-phase signals in the passband and in-phase signals in the stopband. Two Q-enhanced LC resonators are utilized for outphasing. The filter is preceded by a low-noise transconductance amplifier, and it is followed by a programmable gain amplifier and a differential buffer stage for the measurement purposes and gain equalization. The experimental results demonstrate that the voltage gain is tunable between 18 and 47 dB with 0.2 dB steps, which leads to an equalized output power in all the filter configurations. Fabricated in 22 nm Fully Depleted Silicon on Insulator (FD-SOI) technology, the RFFE achieves 4.6 dB NF, -14 dBm IB-IIP3, and 26 dBm IB-IIP2 at 4 GHz. Notably, the fourth-order steep roll-off provides 22 dBm OOB-IIP3 at 2WBW frequency offset. The entire RFFE draws 22-45 mA from a 1 V supply and the filter core occupies 0.11 mm2 chip area.

A D-Band Direct-Conversion IQ Receiver with 28 dB CG and 7.3 dB NF in 130 nm SiGe Process.

In this paper, a D-band direct conversion IQ receiver with on-chip multiplier chain is presented. The D-band LNA with gain-boosting and stagger-tunning technique is implemented to provide high gain and large bandwidth. X9 multiplier chain including Marchand balun and quadrature (90°) hybrid is employed to provide four path LO signal to drive IQ mixer. This receiver is implemented in a 130nm SiGe process and consumes a core area of 1.04 mm2. From the experimental results, the proposed receiver exhibits a 20 GHz bandwidth from 150 GHz to 170 GHz, with CG of 28 dB and NF of 7.3 dB at 158 GHz.

A Passive Wideband Noise-Canceling Mixer-First Architecture With Shared Antenna Interface for Interferer-Tolerant Wake-Up Receivers and Low-Noise Primary Receivers.

Wake-up receivers (WuRX) present an opportunity to reduce average power consumption of IoT transceivers, however achieving sensitivity and interferer tolerance while providing wideband matching and sharing an antenna interface present a significant challenge for existing architectures. This paper presents a primary/WuRX which utilizes a quadrature hybrid coupler based N-Path mixer first architecture to simultaneously achieve low noise, wideband matching and a shared antenna interface. The passive-mixer first approach and a two-code modulated multi-tone signaling scheme provide interferer tolerance in the WuRX. The paper analyzes gain/power trade-offs in the proposed architecture in the context of noise impact with multi-tone WuRX signaling. The proposed architecture is implemented in 65 nm CMOS and occupies 2.25 mm 2. The primary RX achieves 3.8 dB NF and 0.75 dBm out-of-band P1dB with 440μW power consumption. The WuRX achieves -86 dBm sensitivity for 10kb/s data rate and up to -40 dB signal-to-interferer ratio (SIR) with 171μW power consumption.

A 26–31 GHz Linearized Wideband CMOS LNA Using Post-Distortion Technique

This paper presents a modified post-distortion (PD) linearization technique for cascode common-gate low noise amplifiers (CG-LNAs) working at high frequencies up to millimeter-wave band. This technique utilizes an auxiliary transistor together with an inter-stage inductor to suppress the third order distortion without degrading gain. The input third order intercept point (IIP3) of the linearized CG-LNA is improved by a factor of up to 12 dB. For demonstration, an mm-wave differential CG-LNA was fabricated based on a 65-nm CMOS process. It achieves 2.4–10.6 dBm IIP3, 9.6–12 dB gain, 5.0–5.45 dB NF over 26–31 GHz and consumes 14.4 mW from a 1.2 V supply.

A 1–3 GHz CMOS mixer-first receiver frontend with dual-feedback OTA achieving 306 MHz IF bandwidth, 2.1 dB NF, and 33 dB gain

In this paper, a mixer-first receiver frontend with dual-feedback baseband is proposed. The negative resistive and positive capacitive feedback paths are both applied to single-stage inverter-based operational transconductance amplifier (OTA) with fewer poles, to cover a wide BB frequency range. The [Formula: see text]-path filtering at the RF side and second-order filtering at the BB side inhibit out-of-band blocker interferences. The receiver frontend is designed in 65 nm CMOS. Simulation results display an NF of 2.1 dB across 306 MHz IF bandwidth, and a maximum gain of 33 dB from 1 to 3 GHz LO frequency range. The in-band and out-of-band IIP3 are -13 and 16 dBm, respectively. The receiver core draws 40 mW at 1 GHz LO frequency.

Sub-6 GHz Noise-cancelling Balun-LNTA with Dual-band Q-enhanced LC Notch Filter for 5G New Radio Cellular Applications

This paper presents a blocker-tolerant broadband balun-low-noise transconductance amplifier (LNTA) with a high-Q dual-band LC notch filter for 5G new radio (NR) sub-6GHz cellular applications. The proposed balun-LNTA employs a noise-cancelling 1:5 CG-CS balun-LNA topology with local feedback gm-boosting and modified current-bleeding techniques to support entire bands of sub-6 GHz 5G NR application with less than 5 dB NF performance and balanced output of balun-LNTA. The dual-band Q-boosted LC notch filter with a band-switchable differential inductor is also proposed to enhance blocker tolerance of the receiver by removing out-of-band blockers and strong transmitter leakage signals. Simulated in a 65-nm CMOS process, the designed balun-LNTA achieves a minimum noise figure of 2.38 dB, a maximum transconductance gain of 44 mS, an S11 of less than -10 dB over the frequency range of 50 MHz-6 GHz, an input-referred third-order intercept point of 1.82 dBm, and blocker rejection ratios of more than 15 dB. It consumes 5.9 mA from a nominal supply voltage of 1 V. Its active die area is 0.55 mm².

A 1.7–3.6 GHz 20 MHz-Bandwidth Channel-Selection N-Path Passive-LNA Using a Switched-Capacitor-Transformer Network Achieving 23.5 dBm OB-IIP₃ and 3.4–4.8 dB NF

This article reports a channel-selection N-path passive low-noise amplifier (pLNA) featuring only switches, capacitors, and a step-up transformer (i.e. a SCT network) to build a highly linear, frequency-tunable, and high-Q bandpass response with in-band voltage gain and input-impedance matching. We also reveal the inductive and lowpass properties of the step-up transformer, composed of two vertically coupled spiral coils, for passband centering with the local oscillator (LO) frequency, and harmonic-folding reduction. Prototyped in 28 nm CMOS, a 4-path 20 MHz-bandwidth pLNA scores a 9.8 dB voltage gain and a 3.4–4.8 dB NF over a 1.7–3.6 GHz range. At 3 GHz, the out-of-band (OB)-IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> measures +23.5 dBm, and the 3rd-harmonic-folding rejection ratio (HFRR <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) is 33 dB. With a blocker applied at the 80 MHz offset, the blocker −1 dB compression point ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{B}_{-1\,\text {dB}}$ </tex-math></inline-formula> ) attains +1.7 dBm, and the blocker NF only raises moderately to 4.7 dB up to a 0 dBm blocker power. The only dynamic power comes from the four-phase 25%-duty-cycle LO generator that consumes 17.8–38.2 mW between 1.7 and 3.6 GHz. The entire pLNA occupies a 0.84 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die area.

A Reconfigurable Power-Efficient Quantized Analog RF Front-End With Smart Calibration

A power scalable RF front-end using Quantized Analog signal processing is presented. The front-end is based on a voltage-mode power scalable approach which allows the power dissipation to be scaled upon the operative scenario and to performing an agile calibration for mismatch impairments. Power and input dynamic range can be scaled upon the desired 1dBCP (from -15.3dBm to 0.5dBm) while keeping the same sensitivity with 2.5dB NF. Signal path power can vary between 3.3mW to 6.4mW while clock generation and distribution power can vary between 1.6mW/GHz to 18.5mW/GHz, with a PN as low as -171.2dBc/Hz. After calibration, IM2 and IM3 improved up to 33dB while 1dBCP improved by 1dB, which resulted in achieving an IIP3 of 26.1dBm and IIP2 of 71dBm at 0dBm 1dBCP.

A 2.4 GHz sub 1-mW highly linear differential LNA using balun transformer gm-boosting technique

This paper presents a passive gm-boosting differential low noise amplifier (LNA) for low power applications using a single-to-double transformer. This LNA improves noise figure and linearity with no extra power penalty by using the front-end balun together with noise and distortion cancelation. To address the excess power and noise that are introduced by the auxiliary amplifier, both the current reuse and resistive feedback techniques are used. The input balun provides the differential signals from the single ended input signal and boosts the gm of the amplifier. gm-boosting together with the distortion reduction technique improve both the second and third order nonlinearity. The detailed analysis and simulations including Gain, NF, and Linearity in a standard 65nm CMOS technology are given. Simulation results reveal that the LNA achieves over 23.5 dB gain, 2.8 dB NF, IIP3 and IIP2 of +4.3 dBm and +46 dBm, respectively. It consumes 620 µW from a 0.8 V supply voltage while the total effective die area is 0.21mm2.