Data Path Allocation Research Articles

Anycast-Based Optimizations for Inter-Data-Center Interconnections [Invited

The cloud service delivery model is driving the data center (DC) architectural model towards a fully virtualized infrastructure acting as geographically distributed pools of shared resources, dynamically allocated to different services. Such a scenario calls for the anycast routing of virtual machine (VM) migration requests in order to select the destination server where the VMs will be migrated by taking into account the actual load of DC interconnections while addressing VM data transfer requirements. To this purpose, a management platform is presented that enables the dynamic connectivity setup between DCs without a priori indication of the destination server, according to the anycast principle. Specifically, data path allocation policies are proposed to select a proper inter-DC network path, and accordingly a destination server, to allow VM migration data to experience adequate delay performance. Using a simulation approach, the policies are compared in terms of success rate of delay-constrained data path setup as well as in terms of their capability to limit migration delay.

AN EVOLUTIONARY ALGORITHM FOR THE ALLOCATION PROBLEM IN HIGH-LEVEL SYNTHESIS

This paper presents an evolutionary algorithm to solve the datapath allocation problem in high-level synthesis. The method performs allocation of functional units, registers, and multiplexers in addition to controller synthesis with the objective of minimizing the cost of hardware resources. The system handles multicycle functional units as well as structural pipelining. The proposed method was implemented using C++ on a Linux workstation. We tested our method on a set of high-level synthesis benchmarks, all yielding good solutions in a short time. An integration path to Field Programmable Gate Arrays (FPGAs) is provided through VHDL.

A neural networks algorithm for data path synthesis

This paper presents a deterministic parallel algorithm to solve the data path allocation problem in high-level synthesis. The algorithm is driven by a motion equation that determines the neurons firing conditions based on the modified Hopfield neural network model of computation. The method formulates the allocation problem using the clique partitioning problem, an NP-complete problem, and handles multicycle functional units as well as structural pipelining. The algorithm has a running time complexity of O(1) for a circuit with n operations and c shared resources. A sequential simulator was implemented on a Linux Pentium PC under X-Windows. Several benchmark examples have been implemented and favorable design comparisons to other synthesis systems are reported.

Interconnection optimization in data path allocation using minimal cost maximal flow algorithm

In most designs of digital systems, as the area taken up by multiplexers and wires outweighs that of functional modules and registers, the interconnection optimization in high-level synthesis becomes very significant. In this paper, a layout area estimation model based on bit-sliced standard cell design style is presented. With the model, a data path allocation system was developed to optimize the interconnection. Both the module allocation problem and the register allocation problem are modeled as the minimal cost maximal flow problem in a network. Experimental results show that the layout area estimation model is suitable to guide the design decisions during the allocation and good designs with optimal interconnections can be produced by the system.

Optimal datapath allocation for multiple-wordlengthsystems

High-level synthesis for multiple-wordlength systems is examined. A formulation of the combined scheduling, binding, and wordlength selection problem is proposed. Integer linear programming is used to obtain area-optimal scheduling, binding and wordlength selection for such systems.

A flexible datapath allocation method for architectural synthesis

We present a robust datapath allocation method that is flexible enough to handle constraints imposed by a variety of target architectures. Key features of this method are its ability to handle accurate modeling of datapath units and the simultaneous optimization of direct objective functions. The proposed method consists of a new binding model construction scheme and an optimization technique based on simulated annealing. To illustrate the flexibility of this method, two datapath allocation procedures have been developed for two problem enviroments: (1) a procedure that incorporates interconnection area and delay estimates, where floor-planning is tightly integrated into datapath allocation; and (2) a procedure that handles registers, register files, and multiport memories for data storage, as well as random and linear topologies for interconnection architectures. Results from these two applications show our method produces competitive designs for benchmark circuits, as well as being flexible enough to be used for a variety of different domains.

Unified data path allocation and BIST intrusion

This paper deals with an approach to the automatic synthesis of self-testable data paths. A self-testable data path contains some test registers that increase its area. Classical approaches synthesizing minimum area data paths and then adding minimum number of test registers to it do not lead to data paths with minimum global area. Testability consideration during synthesis makes design search more efficient and hence can possibly find self-testable data paths with minimum area. We present a model to evaluate the testability of data paths that is used when data path allocation is being done. Moreover, we propose some heuristics that guide the design space search during allocation, to save exploration time. When each allocation decision has to be made, an implementation alternative is chosen according to the area and testability increments that the alternative produces, so that the area is only increased when the testability gain is worth it.

Allocation Techniques for Reducing BIST Area Overhead ofData Paths

Built-in self-test (BIST) techniques modify functional hardware so that a chip has the capability to test itself. A prime concern in using BIST is the area overhead due to the modification of normal registers to BIST registers. This paper proposes register and interconnect assignment techniques that address the BIST area overhead issue during high-level synthesis. A minimal intrusion BIST methodology is employed where a subset of the functional registers are modified to be BIST registers. Depending on the BIST functions performed (test pattern generation and/or test response compression) and the concurrency of the functions, four types of BIST registers with varying costs are used. Data path allocation techniques are presented that (1) maximize the sharing of BIST registers between modules, and (2) minimize the number of expensive BIST registers that are essential for minimal intrusion BIST of a data path. The designs synthesized by our techniques have the same number of functional modules and registers as those synthesized using traditional approaches but require significantly lower BIST area overhead.

Using time zones for data path allocation in high-level synthesis of digital systems

Abstract The paper describes the data path allocation in high-level synthesis of digital systems using a new approach named the time-zone approach. Using the time-zone approach, where lime steps are partitioned into zones, the register allocation and the module allocation for a given scheduled data flow graph (DFG) are performed in the same phase. The number of registers required to store the values in the DFG is minimized, and at the same time the interconnections between the registers and the modules (as well as the number of multiplexers required) are optimized. The experimental results obtained from testing several published benchmarks show that the allocation results are improved in terms of reduction of interconnections and the number of multiplexers and registers.

Data path synthesis

This paper reviews all the phases in data path synthesis: register allocation, storage grouping, module allocation and interconnect allocation. In addition, a new phase for the storage value insertion is introduced. For each of these phases a formal problem description is given. Restrictions on the data path allocation phases are presented, which delimit the problems to cases which can be solved by polynomial algorithms. For the general cases, heuristics are provided which have appeared to be effective in the literature. Special data path architectures may require special algorithms to make use of their features. Throughout the paper archetectural constraints are described and effective algorithms for them derived. To construct an effective data path allocation system, a scheme has to be defined. The scheme determines which subproblems are solved in what order and which constraints are taken into account in each phase. The data flow graph and schedule and their match with the data path architecture have a major impact on the development of a scheme. This paper will point out the trade-offs that have to be made when developing such a scheme. This paper provides a reference to most of the data path allocation algorithms published in the scope of high-level synthesis. Most of the techniques are explained in considerable detail and various examples are given. The paper comments on the applicability of most of the algorithms for particular data path allocation problems.

Automated transformation of algorithms into register-transfer level implementations

This paper describes a high-level synthesis system, called CAMAD, for transforming algorithms into hardware implementation structures at register-transfer level. The algorithms are used to specify the behaviors of the hardware to be designed. They are first translated into a formal representation model which is based on timed Petri nets and consists of separate but related descriptions of control and data path. The formal model is used as an intermediate design representation and supports an iterative transformation approach to high-level synthesis. The basic idea is that once the behavioral specification is translated into the initial design representation, it can be viewed as a primitive implementation. Correctness-preserving transformations are then used to successively transform the initial design into an efficient implementation. Selection of transformations is guided by an optimization strategy which makes design decisions concerning operation scheduling, data path allocation, and control allocation simultaneously. The integration of these several synthesis subtasks has resulted in a better chance to reach the globally optimal solution. Experimental results show that our approach produces improved register-transfer designs, especially in the cases when the designed hardware consists of data paths and control logics that are tightly coupled.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A comparison study of minimization methods of unit interconnection in VLIW processors

Previous studies have shown the significant part of the interconnection optimization in architecture synthesis. During this process, operator allocation to functional units is done, followed by a data path allocation phase which consists in minimizing the numbers of registers, multiplexers and physical links. We propose, in this paper, to describe briefly four methods to solve the data path allocation problem and to compare their efficiencies on scalar and vector algorithms. Three methods consist in already published techniques and the fourth is a new procedure based on the maximum compatible mechanism.

New methods for coloring and clique partitioning in data path allocation

The EGAD data path allocation system is investigating the use of coloring of conflict graphs and clique partitioning of compatibility graphs to allocate operations onto functional units, values into registers, and data transfes onto interconnect. This work is a part of the high-level synthesis effort at Carnegie Mellon University, called the System Architect's Workbench. The least cost clique partitioning and coloring problems have been widely used for data path allocation in high-level synthesis. This paper describes research areas important to writing good data path allocation heuristics. A new approach to modeling cost based on set inclusion, and a technique for estimating the quality of solutions based on the duality theorem of linear programming are presented.

Design of clocking schemes in high-level synthesis

This paper describes an performance-driven optimization approach to high-level synthesis of VLSI systems. In particular, it presents a new algorithm to automatically design clocking schemes for digital VLSI systems. An optimization strategy is used to integrate the clocking scheme design process with the rest of the high-level synthesis sub-tasks, such as data path allocation, control allocation, module binding and system partitioning. The main features of our approach are the integration of the clock design with other synthesis activities and an ability to generate asynchronous clocking schemes by partitioning VLSI systems into time-independent modules.

FLORA: A data path allocator based on branch-and-bound search

We propose for the data path allocation problem a new approach based on a branch-and-bound search algorithm. A novel target architecture originated from RISC research is used to reduce both the storage requirement and the clock cycle length. We verticaly divide the problem into three subtasks: operation assignment, storage allocation, and data transfer binding. The branch-and-bound search is applicable to every subtask. To speed up the search, we derive cost functions which accurately estimate both the storage and interconnection requirements. The proposed approach has been implemented in a tool called FLORA. The strenght of our approach is demonstrated through experiments.

Integration of algorithmic VLSI synthesis with testability incorporation

A VLSI design synthesis approach with testability, area, and delay constraints is presented. This research differs from other synthesizers by implementing testability as part of the VLSI design solution. A binary-tree data structure is used throughout the testable design search. Its bottom-up and top-down algorithms provide data-path allocation, constraint estimation, and feedback for design exploration. The partitioning and two-dimensional characteristics of the binary-tree structure provide VLSI design floorplans and global information for test incorporation. A differential equation and elliptical wave filter example were used to illustrate the design synthesis with testability constraints methodology. Test methodologies such as multiple-chain scan paths and BIST (built-in self-test) with different test schedules were explored. Design scores comprised of area, delay, fault coverage, and test time were computed and graphed. >