Data Vortex Switch Research Articles

An efficient and improved algorithm for generating an equivalent planar architecture of the data vortex switch

The data vortex (DV) switch was originally designed as an all optical interconnection network for high performance computing (HPC) applications. It was highly scalable with low latency and high throughput, compared to traditional switches used for optical packet switching (OPS) and HPC applications. The equivalent planar (chained MIN) model of the DV, proposed in previous literature, is a planar diagrammatic conversion of a 3-D model of the DV network. In this paper, we will focus on exploring a new, efficient and improved generalized algorithm that enables the arrangement of routing pathways to be implemented as an equivalent planar architecture (EPA, chained MIN) of a DV to find all possible routes between each source and target node pair. The original 3-D architecture of any size can be converted to a planar structure more simply by using the new generalized equivalent planar architecture (EPA) algorithm. To verify the proposed EPA algorithm, it was tested with different input traffic loads and network sizes while keeping the active angle ‘A’ constant. Network performance parameters, including injection rate (throughput) and latency (mean hops), obtained from simulation results are also provided to confirm the validity of the proposed EPA algorithm. This new algorithm is versatile, simple and can be applied to networks of various sizes.

All-Optical Data Vortex Node Using an MZI-SOA Switch Array

We propose and demonstrate a new structure of a Data Vortex switch node for all-optical routing of wavelength-division-multiplexing (WDM) 10-Gb/s optical packets. The proposed node consists of two Mach-Zehnder interferometers with integrated semiconductor optical amplifier: an optical and gate and a high-speed optical switch. In the experiment, WDM 10-Gb/s data packets are successfully routed with 1-dB power penalty at a bit-error rate of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-9</sup> .

Performance evaluation of the augmented data vortex switch fabric: An all-optical packet switched interconnection network

Modern high-performance computing systems require networks with high capacity, extremely high throughput and low latency in order to pass messages between thousands of processors and memory elements. Optical Interconnection Networks (OIN) offer a potentially viable solution to this requirement. An all-optical packet switched interconnection network called a Data Vortex (DV) switch has already been proposed by Yang et al. for the purpose of large scale photonic interconnections. For any interconnection network, fault tolerance and reliability are crucial issues, evaluation of which lacked attention for the case of the DV switch. In our earlier work we therefore presented the results for fault tolerance and reliability analysis of the primary DV switch. We also proposed a new Augmented Data Vortex (ADV) switch fabric, to improve the fault tolerance of the primary DV switch. The performance as regards fault tolerance of the ADV switch was computed and detailed results were obtained. In this paper, performance of ADV is investigated with reference to parameters such as latency and injection ratio (throughput) by means of numerical simulations. A uniform random traffic model has been used for the performance evaluation. The results obtained are compared with the results reported for the DV switch. The results show that the ADV switch with enhanced fault tolerance also improves the performance regarding latency. For same switch sizes (i.e. the same number of angles A , and height H ) the injection ratios (throughput) for the DV and the ADV switches are comparable. Hence it can serve as a suitable candidate for high performance computing.

The augmented data vortex switch fabric: An all-optical packet switched interconnection network with enhanced fault tolerance

Optical Multistage Interconnection Networks (OMINs) are capable of transmitting terabits of bandwidth per second, and they have been considered as possible solutions to the electronic communications bottleneck in interconnection networks. A novel architecture, the Data Vortex (DV) switch, has been proposed by Yang et al., as a scalable, ultra low latency, ultra high capacity, high throughput, low cross-talk and low BER, all-optical packet switching fabric that is a suitable candidate for use as an OMIN. For any interconnection network, its fault tolerance and reliability are crucial issues, which have lacked attention up to now in the case for a DV switch. In this paper we, therefore, present results of fault tolerance and reliability analysis of the primary DV switch, and propose (1) a new Augmented Data Vortex (ADV) switch fabric, to improve the fault tolerance of the primary DV switch. (2) The labelling and a numbering scheme, with detailed interconnections of nodes for the ADV switch is given. (3) A new self-routing procedure and a priority scheme for distributed control signalling in the ADV switch have been given. (4) For the first time, conversion of the 3-dimensional switch to an equivalent chained-MIN model, has been given, which is more suitable for later analysis of fault tolerance. (5) A multiplexing scheme at input ports and output ports which further enhances the fault tolerance of the ADV switch has been given. (6) Computation has been done of the reliability and fault tolerance of the new architecture via an analytical model. (7) Finally, comparison of the ADV switch architecture with the primary architecture (DV) in view of fault tolerance and reliability has been given, and hardware complexity and cost effectiveness have been studied.

Ultra-high throughput data vortex network with redundant routing and control paths

Additional routing and control paths are proposed to improve throughput performance in data vortex switch networks. The simulation study confirms that ultra-low injection blocking rate can be achieved with the modified routing and control scheme.

Improved performance using shortcut path routing within data vortex switch network

Shortcut path routing is proposed for large-scale data vortex switch networks. The simulation study shows for worst traffic scenarios that such a routing scheme helps to improve both throughput and latency performance.

Performances of the Data Vortex switch architecture under nonuniform and bursty traffic

The Data Vortex switch architecture has been proposed as a scalable low-latency interconnection fabric for optical packet switches. This self-routed hierarchical architecture employs synchronous timing and distributed traffic-control signaling to eliminate optical buffering and to reduce the required routing logic, greatly facilitating a photonic implementation. In previous work, we have shown the efficient scalability of the architecture under uniform and random traffic conditions while maintaining high throughput and low-latency performance. This paper reports on the performance of the Data Vortex architecture under nonuniform and bursty traffic conditions. The results show that the switch architecture performs well under modest nonuniform traffic, but an excessive degree of nonuniformity will severely limit the scalability. As long as a modest degree of asymmetry between the number of input and output ports is provided, the Data Vortex switch is shown to handle very bursty traffic with little performance degradation.

WDM packet routing for high-capacity data networks

We present experimental and numerical studies of a novel packet-switch architecture, the data vortex, designed for large-scale photonic interconnections. The selfrouting multihop packet switch efficiently scales to large port counts (>10 k) while maintaining low latencies, a narrow latency distribution, and high throughput. To facilitate optical implementation, the data-vortex architecture employs a novel hierarchical topology, traffic control, and synchronous timing that act to reduce the necessary routing logic operations and buffering. As a result of this architecture, all routing decisions for the data packets are based on a single logic operation at each node. The routing is further simplified by the employment of wavelength division multiplexing (WDM)-encoded header bits, which enable packet-header processing by simple wavelength filtering. The packet payload remains in the optical domain as it propagates through the data-vortex switch fabric, exploiting the transparency and high bandwidths achievable in fiber optic transmission. In this paper, we discuss numerical simulations of the data-vortex performance and report results from an experimental investigation of multihop WDM packet routing in a recirculating test bed.