Data Speculation Research Articles

SCA-LFD: Side-Channel Analysis-Based Load Forecasting Disturbance in the Energy Internet

The energy Internet (EI) equipment may face threats that attackers poison federated learning (FL) models to disturb electricity load forecasting. To mitigate this vulnerability, it is important to study load forecasting disturbance approaches. This article proposes a side-channel analysis (SCA)-based disturbance approach. First, we design an FL SCA scheme to extract power information from the FL chip running forecasting model. Second, we propose an FL data speculation method using an optimized convolutional neural network trained with SCA information. Third, we design a label-flipping-based poisoning scheme with speculated data characteristics for load forecasting disturbance. Experimental results show attackers can successfully poison and disturb FL-based load forecasting. The average accuracy of EI load data speculation is 99.8%. This work is the first to study EI load forecasting disturbance from an SCA perspective.

Digital revolution for the agroecological transition of food systems: A responsible research and innovation perspective

CONTEXTSo far, digital technology development in agriculture has mainly dealt with precision agriculture, often associated with conventional large-scale systems. The emergence of digital agriculture - based on the triptych of “new data sources / new processing methods / new inter-connection capacities (internet)” - opens up prospects for mobilizing digital technologies to accelerate the deployment of other forms of agriculture, such as agroecology. A specific research agenda must therefore be built to redirect researchers specialized in digital technologies towards these new issues. This construction is significant because digital technology and agroecology are disruptive innovations that shake up the actors' practices, agricultural innovation ecosystems, and value chains. OBJECTIVEAn interdisciplinary group of INRAE researchers (covering 10 scientific departments) was mandated to carry out this reflection, with the objective of developing a research agenda to better couple digitalization and agroecology, in order to pave the way for responsible digital farming. The group used the framework of responsible research and innovation. METHODOver 18 months, the group met monthly by video-conference, to overcome the interdisciplinarity barrier, and at three face-to-face seminars, where creative design exercises were carried out (based on a world café format, and “remember the future” method). This work gave rise to three prospective lines of research aimed at putting digitalization at the service of agroecology and local food systems. These topics prioritize research that fosters innovations in digital technology, as well as organisations and policies that (1) accelerate the agroecological transition on the farm and in the territories, (2) manage the territories as commons, (3) empower farmers and consumers. Then, the group examined these three prospective lines of research from an RRI perspective as well as three current research topics on digital agriculture (digital soil mapping, precision agriculture, technologies for food wastage reduction). RESULTS AND CONCLUSIONSThis work allowed us to highlight the gaps between current research on digital agriculture and the RRI expectations, and the tensions (between rationalization and diversity of farming systems, between complexity of agroecological systems and the need for simplification of models, and finally between data speculation and frugality). We were also able to refine the specific scientific questions of each prospective line of research and finally to draw attention to the key levers that will have to be integrated if these research efforts are to be approached from an RRI perspective. SIGNIFICANCEThis contribution shows RRI can be used not only to reflect on research practices but also as a framework to build a research agenda paving the way for responsible digital agriculture.

New bracket and motion control system for distributed photovoltaic power stations

In view of the existing solar panel blackout, affecting the ecological environment, unreasonable spatial distribution, low power generation efficiency, high failure rate, difficult to operate and other issues, design a mechanical uniform solar power bracket: weather conditions, temperature, light strength and other multi-factor evaluation of the way to monitor the state of photovoltaic panels to adjust. According to the latitude and longitude and terrain of photovoltaic plate installation, the periodic movement trajectory is automatically planned, the operation is monitored centrally, and the failure point is located quickly and the operational efficiency is improved by comparing with big data speculation.

Shared write buffer to boost applications on SpMT architecture

With the trend of growing number of integrated processing cores on Chip Multiprocessors, researchers are working hard to increase the available parallelism of software programs so as to efficiently harness the growing computing power. One noticeable direction among these efforts is speculative multi-threading (SpMT), a.k.a thread level speculation, which aims to extract thread level parallelism by splitting a sequential execution thread into several finer ones and execute them on parallel. A SpMT thread is in speculative status before it “knows” all its input data are correct. A speculative thread needs to write to the L1 cache, but its output might be discarded if the speculation eventually fails. However, another speculative thread may have already read in such speculative output. Therefore, some mechanism is needed to support speculative read and write. And because the SpMT threads are extracted from a single thread, they usually share lots of data, thus there might be intense data coherence among the L1 caches. It would be very complicated to support data coherence and speculation together. This Paper proposes a shared write buffer among the SpMT cores. We are able to confine the speculative read and write in the SWB, thus the speculation will not interference with coherence, and the L1 cache design could be drastically simplified. Experiments show that the SWB can capture a big portion of inter-core data sharing, reduce cache coherence, and drastically improve data access performance of SpMT threads.

Exploring energy-performance-quality tradeoffs for scientific workflows with in-situ data analyses

Power and energy are critical concerns for high performance computing systems from multiple perspectives, including cost, reliability/resilience and sustainability. At the same time, data locality and the cost of data movement have become dominating concerns in scientific workflows. One potential solution for reducing data movement costs is to use a data analysis pipeline based on in-situ data analysis.However, the energy-performance-quality tradeoffs impact of current optimizations and their overheads can be very hard to assess and understand at the application level.In this paper, we focus on exploring performance and power/energy tradeoffs of different data movement strategies and how to balance these tradeoffs with quality of solution and data speculation. Our experimental evaluation provides an empirical evaluation of different system and application configurations that give insights into the energy-performance-quality tradeoffs space for in-situ data-intensive application workflows. The key contribution of this work is a better understanding of the interactions between different computation, data movement, energy, and quality-of-result optimizations from a power-performance perspective, and a basis for modeling and exploiting these interactions.

Remarks on “Piezonuclear neutrons from fracturing of inert solids”

Carpinteri et al. [F. Cardone, A. Carpinteri, G. Lacidogna, Physics Letters A 373 (2009) 4158] reported that by the sudden fracture of granite blocks under pressure P ⩾ 94.4 MPa ejects a stream of neutrons catch by a 3He detector and displayed by a “BD” dosimeter. As claimed, these neutrons come from the fission reaction Fe 56 → 2 ( Al 27 + n ) being the compound Fe 2O 3 present at 3% in granite. We would like to point out the inconsistency of this endothermic nuclear reactions. No gamma rays measurements associated with any nuclear reactions and no radioactive isotopes in fractured granite blocks are reported. It is claimed strictly radiation-less reactions (except for the neutrons). Our remarks are related to the incompleteness of experimental set-up and data speculation. Mistake in the analysis of neutron detection due to intense acoustic signal or charged particle emitted in fractoemission phenomena is suggested.

Lazy and speculative execution in computer systems

The distinction between lazy and eager (or strict) evaluation has been studied in programming languages since Algol 60's call by name, as a way to avoid unnecessary work and to deal gracefully with infinite structures such as streams. It is deeply integrated in some languages, notably Haskell, and can be simulated in many languages by wrapping a lazy expression in a lambda. Less well studied is the role of laziness, and its opposite, speculation, in computer systems, both hardware and software. A wide range of techniques can be understood as applications of these two ideas. Laziness is the idea behind: Redo logging for maintaining persistent state and replicated state machines: the log represents the current state, but it is evaluated only after a failure or to bring a replica online. Copy-on-write schemes for maintaining multiple versions of a large, slowly changing state, usually in a database or file system. Write buffers and writeback caches in memory and file systems, which are lazy about updating the main store. Relaxed memory models and eventual consistency replication schemes (which require weakening the spec). Clipping regions and expose events in graphics and window systems. Carry-save adders, which defer propagating carries until a clean result is needed. "Infinity" and "Not a number" results of floating point operations. Futures (in programming) and out of order execution (in CPUs), which launch a computation but are lazy about consuming the result. Dataflow is a generalization. "Formatting operators" in text editors, which apply properties such as "italic" to large regions of text by attaching a sequence of functions that compute the properties; the functions are not evaluated until the text needs to be displayed. Stream processing in database queries, Unix pipes, etc., which conceptually applies operators to unbounded sequences of data, but rearranges the computation when possible to apply a sequence of operators to each data item in turn. Speculation is the idea behind: Optimistic concurrency control in databases, and more recently in transactional memory Prefetching in memory and file systems. Branch prediction, and speculative execution in general in modern CPUs. Data speculation, which works especially well when the data is cached but might be updated by a concurrent process. This is a form of optimistic concurrency control. Exponential backoff schemes for scheduling a resource, most notably in LANs such as WiFi or classical Ethernet. All forms of caching, which speculate that it's worth filling up some memory with data in the hope that it will be used again. In both cases it is usual to insist that the laziness or speculation is strictly a matter of scheduling that doesn't affect the result of a computation but only improves the performance. Sometimes, however, the spec is weakened, for example in eventual consistency. I will discuss many of these examples in detail and examine what they have in common, how they differ, and what factors govern the effectiveness of laziness and speculation in computer systems.

Recovery code generation for general speculative optimizations

A general framework that integrates both control and data speculation using alias profiling and/or compiler heuristic rules has shown to improve CPU2000 performance on Itanium systems. However, speculative optimizations require check instructions and recovery code to ensure correct execution when speculation fails at runtime. How to generate check instructions and their associated recovery code efficiently and effectively is an issue yet to be well studied. It is also, very important that the recovery code generated in the earlier phases integrate gracefully in the later optimization phases. At the very least, it should not hinder later optimizations, thus, ensuring overall performance improvement. This paper proposes a framework that uses an if-block structure to facilitate check instructions and recovery code generation for general speculative optimizations. It allows speculative instructions and their recovery code generated in the early compiler optimization phases to be integrated effectively with the subsequent optimization phases. It also allows multilevel speculation for multilevel pointers and multilevel expression trees to be handled with no additional complexity. The proposed recovery code generation framework has been implemented and evaluated in the Open Research Compiler (ORC).

Simultaneous multithreading trace processors: Improving trace processors performance

Trace Processors is a promising next-generation microarchitecture that exploits implicit thread-level parallelism (TLP) in conventional applications by employing aggressive control and data speculation techniques. Although high performance can be achieved by trace processors, but in fact, processing element (PE) resources are still underutilized due to frequent trace cache misses and next-trace mispeculations. When trace cache miss occurs, trace dispatch engine must stall and supply nothing to idle PE until the completion of trace construction. When next-trace mispeculation occurs, in addition to trace dispatch engine stall, all speculative execution results after the mispeculated trace must be discarded. All the operations on those squashed traces are useless. When trace processors scales up with more PEs, this problem will become more severe. Addressing to this problem, we propose augmenting multiple thread contexts into trace processors. A combined microarchitecture—Simultaneous Multithreading trace processors (SMT trace processors) is proposed in this paper. By dispatching trace from other threads, the penalties of trace cache miss and next-trace mispeculation can be tolerated. Introducing multiple thread contexts reduce the percentage of wrong-path speculations for each thread and improve PE execution efficiency significantly. Simulation results show that integrating two thread contexts can improve 8-PE trace processors performance 27.7%. When augmenting four and eight thread contexts, the corresponding improvements are 28.7 and 15.4%. And we believe that even higher performance improvement can be expected when we integrate more PEs into SMT trace processors.

Interprocedural probabilistic pointer analysis

When performing aggressive optimizations and parallelization to exploit features of advanced architectures, optimizing and parallelizing compilers need to quantitatively assess the profitability of any transformations in order to achieve high performance. Useful optimizations and parallelization can be performed if it is known that certain points-to relationships would hold with high or low probabilities. For instance, if the probabilities are low, a compiler could transform programs to perform data speculation or partition iterations into threads in speculative multithreading, or it would avoid conducting code specialization. Consequently, it is essential for compilers to incorporate pointer analysis techniques that can estimate the possibility for every points-to relationship that it would hold during the execution. However, conventional pointer analysis techniques do not provide such quantitative descriptions and, thus, hinder compilers from more aggressive optimizations, such as thread partitioning in speculative multithreading, data speculations, code specialization, etc. We address this issue by proposing a probabilistic points-to analysis technique to compute the probability of every points-to relationship at each program point. A context-sensitive interprocedural algorithm has been implemented based on the iterative data flow analysis framework, and has been incorporated into SUIF and MachSUIF. Experimental results show this technique can estimate the probabilities of points-to relationships in benchmark programs with reasonable small errors, about 4.6 percent on average. Furthermore, the current implementation cannot disambiguate heap and array elements. The errors are further significantly reduced when the future implementation incorporates techniques to disambiguate heap and array elements.

A compiler framework for speculative optimizations

Speculative execution, such as control speculation or data speculation, is an effective way to improve program performance. Using edge/path profile information or simple heuristic rules, existing compiler frameworks can adequately incorporate and exploit control speculation. However, very little has been done so far to allow existing compiler frameworks to incorporate and exploit data speculation effectively in various program transformations beyond instruction scheduling. This paper proposes a speculative static single assignment form to incorporate information from alias profiling and/or heuristic rules for data speculation, thus allowing existing frameworks to be extended to support both control and data speculation. Such a general framework is very useful for EPIC architectures that provide run-time checking (such as advanced load address table ) on data speculation to guarantee the correctness of program execution. We use SSAPRE as one example to illustrate how to incorporate data speculation in partial redundancy elimination, register promotion, and strength reduction. Our extended framework allows both control and data speculations to be performed on top of SSAPRE and, thus, enables more aggressive speculative optimizations. The proposed framework has been implemented on Intel's Open Research Compiler. We present experimental data on some SPEC2000 benchmark programs to demonstrate the usefulness of this framework.

The compiler as a validation and evaluation tool

Like a processor executes flawlessly at different frequencies, a compiler should produce correct results at any optimization level. The Intel® Itanium® processor family with its new features, like the register stack engine and control- and data speculation, provides new and unique challenges for ported software and compiler technology. This paper describes validation and evaluation techniques that can be employed in compilation tools and can help to get a cleaner port of an application, a more robust compilation system and even insights into performance tuning opportunities. Using Itanium as a specific example, the paper explains why the register stack engine (RSE), the large register file, or control- and data speculation can potentially expose bugs in poorly written or compiled software. It then demonstrates validation and evaluation techniques to find or expose these bugs. An evaluation team can employ them to find, eliminate and evaluate software bugs. A compiler team can use them to make the compiler more stable and robust. A performance analysis team can use them to uncover performance opportunities in an application. We demonstrate our validation and evaluation techniques on code examples and provide run-time data to indicate the cost of some of our methods.

Thread partitioning and value prediction for exploiting speculative thread-level parallelism

Speculative thread-level parallelism has been recently proposed as a source of parallelism to improve the performance in applications where parallel threads are hard to find. However, the efficiency of this execution model strongly depends on the performance of the control and data speculation techniques. Several hardware-based schemes for partitioning the program into speculative threads are analyzed and evaluated. In general, we find that spawning threads associated to loop iterations is the most effective technique. We also show that value prediction is critical for the performance of all of the spawning policies. Thus, a new value predictor, the increment predictor, is proposed. This predictor is specially oriented for this kind of architecture and clearly outperforms the adapted versions of conventional value predictors such as the last value, the stride, and the context-based, especially for small-sized history tables.

A compiler framework for speculative analysis and optimizations

Speculative execution, such as control speculation and data speculation, is an effective way to improve program performance. Using edge/path profile information or simple heuristic rules, existing compiler frameworks can adequately incorporate and exploit control speculation. However, very little has been done so far to allow existing compiler frameworks to incorporate and exploit data speculation effectively in various program transformations beyond instruction scheduling. This paper proposes a speculative SSA form to incorporate information from alias profiling and/or heuristic rules for data speculation, thus allowing existing program analysis frameworks to be easily extended to support both control and data speculation. Such a general framework is very useful for EPIC architectures that provide checking (such as advanced load address table (ALAT) [10]) on data speculation to guarantee the correctness of program execution. We use SSAPRE [21] as one example to illustrate how to incorporate data speculation in those important compiler optimizations such as partial redundancy elimination (PRE), register promotion, strength reduction and linear function test replacement. Our extended framework allows both control and data speculation to be performed on top of SSAPRE and, thus, enables more aggressive speculative optimizations. The proposed framework has been implemented on Intel's Open Research Compiler (ORC). We present experimental data on some SPEC2000 benchmark programs to demonstrate the usefulness of this framework and how data speculation benefits partial redundancy elimination.

Evaluating the impact of reissued instructions on data speculative processor performance

In this paper, we investigate the impact of instructions reissued due to misspeculated data dependences on processor performance. Recently, the practice of speculation in resolving data dependences has been studied as a means of extracting more instruction level parallelism. When a misspeculation occurs, it is necessary to revert the processor state to a safe point where the speculation is initiated, with an instruction reissue mechanism utilized for that purpose. The instruction reissue suffers less miss penalties than instruction squashing which handles misspeculated control flows in current generation processors, but causes redundant instruction dispatching, i.e. multiple copies of an instruction are in flight in functional units. The effectiveness of data speculation would be diminished, if reissued instructions caused serious structural hazards. Therefore, we evaluate how the instruction reissue affects processor performance using an execution-driven simulator. We find that overhead due to instruction reissue is sufficiently small so as to allow data speculation to contribute to processor performance.

Dynamic techniques for load and load-use scheduling

Modern microprocessors employ dynamic instruction scheduling to select independent instructions for parallel execution. Good scheduling of loads is crucial, since the long latency of some loads makes them likely to degrade performance. A good scheduler attempts to issue loads as early as possible. Scheduling loads is not simple. First, safely resolving a load's input dependences can be done only at execution time, after the load address and all previous store addresses are known. Second, varying load latency makes it difficult to prioritize loads and to efficiently schedule load-dependent instructions. This paper surveys several techniques that optimize load scheduling. Memory disambiguation resolves store-load dependences and enables earlier execution of store-independent loads. Memory renaming and memory bypassing short-circuit memory to streamline the passing of values from stores to loads. Critical path scheduling, pre-execution, and address prediction advance long-latency loads by computing load addresses early, or predicting them. Value prediction short-circuits load execution by predicting the loaded data values. Finally, data speculation and hit-miss prediction help the scheduling of load-dependent instructions.

OS and compiler considerations in the design of the IA-64 architecture

Increasing demands for processor performance have outstripped the pace of process and frequency improvements, pushing designers to find ways of increasing the amount of work that can be processed in parallel. Traditional RISC architectures use hardware approaches to obtain more instruction-level parallelism, with the compiler and the operating system (OS) having only indirect visibility into the mechanisms used.The IA-64 architecture [14] was specifically designed to enable systems which create and exploit high levels of instruction-level parallelism by explicitly encoding a program's parallelism in the instruction set [25]. This paper provides a qualitative summary of the IA-64 architecture features that support control and data speculation, and register stacking. The paper focusses on the functional synergy between these architectural elements (rather than their individual performance merits), and emphasizes how they were designed for cooperation between processor hardware, compilers and the OS.

OS and compiler considerations in the design of the IA-64 architecture

Increasing demands for processor performance have outstripped the pace of process and frequency improvements, pushing designers to find ways of increasing the amount of work that can be processed in parallel. Traditional RISC architectures use hardware approaches to obtain more instruction-level parallelism, with the compiler and the operating system (OS) having only indirect visibility into the mechanisms used.The IA-64 architecture [14] was specifically designed to enable systems which create and exploit high levels of instruction-level parallelism by explicitly encoding a program's parallelism in the instruction set [25]. This paper provides a qualitative summary of the IA-64 architecture features that support control and data speculation, and register stacking. The paper focusses on the functional synergy between these architectural elements (rather than their individual performance merits), and emphasizes how they were designed for cooperation between processor hardware, compilers and the OS.

OS and compiler considerations in the design of the IA-64 architecture

Increasing demands for processor performance have outstripped the pace of process and frequency improvements, pushing designers to find ways of increasing the amount of work that can be processed in parallel. Traditional RISC architectures use hardware approaches to obtain more instruction-level parallelism, with the compiler and the operating system (OS) having only indirect visibility into the mechanisms used.The IA-64 architecture [14] was specifically designed to enable systems which create and exploit high levels of instruction-level parallelism by explicitly encoding a program's parallelism in the instruction set [25]. This paper provides a qualitative summary of the IA-64 architecture features that support control and data speculation, and register stacking. The paper focusses on the functional synergy between these architectural elements (rather than their individual performance merits), and emphasizes how they were designed for cooperation between processor hardware, compilers and the OS.

Quantitative evaluation of pipelining and decoupling a dynamic instruction scheduling mechanism

As instruction window size increases, it becomes difficult to maintain processor cycle time. Pipelining the window is not a solution, since it is said that it affects processor performance seriously. However, the pipelining has not been evaluated quantitatively. On the other hand, recent interests on data speculation demand to increase the window size to realize instruction reissue mechanism which deals with misspeculations. For reducing the window size with maintaining the instruction reissue capability, we propose to decouple the reissue mechanism from the scheduling mechanism. Based on simulations, we have evaluated the pipelining and the decoupling of the instruction window.