Datapath Operations Research Articles

A Novel Paradigm of CORDIC-Based FFT Architecture Framed on the Optimality of High-Radix Computation

‘Fast Fourier transform’ (FFT), being a prevalent algorithm for the proficient computation of ‘discrete Fourier transform,’ constitutes one of the major sub-modules in numerous real-time signal processing systems. In this article, a new approach of CORDIC-based high-radix FFT architecture has been demonstrated. Having identified the complex rotation as the most time-consuming elementary operation of FFT, the number of such complex rotations has been optimized by adopting radix-8-based FFT computation. To add to this, CORDIC is employed to realize the complex rotation, keeping aside its multiplier–accumulator (MAC)-based counterpart, for further economizing the VLSI implementation of the proposed FFT architecture. Furthermore, the requirement of CORDIC blocks for last three stages of radix-8 FFT computation has totally been mitigated by utilizing SCALE blocks as the rotation in those stages can be expressed in terms of $$\pi /4$$ or its multiples. RAM is arranged in the form of memory banks to provide parallel data path operations, and RAM switching is performed in between stages for sustaining continuous data flow circumventing data access hazards. The throughput of the proposed radix-8 architecture is eight outputs per clock cycle, while the maximum clock frequency is limited only by the propagation delay of an adder. Hardware utilization and comparative performance evaluation have been reported to prove the proposed architecture’s supremacy. Our proposed prototype radix-8 architecture has been successfully implemented on Zynq UltraScale+ FPGA using Xilinx Vivado 18.2 software for verifying its feasibility in practical applications.

Fine-Grain Back Biasing for the Design of Energy-Quality Scalable Operators

Energy-quality scalable systems are a promising solution to cope with the small energy budgets and high processing demands of mobile and Internet of Things applications. These systems leverage the error resilience of applications to obtain high energy efficiency, at the expense of tolerable reductions in the output quality. Hardware datapath operators able to reconfigure their precision and power consumption at runtime are key components of such systems. However, most implementations of these operators require manual, architecture-specific modifications and tend to have large power overheads compared to standard designs, when working at maximum precision. One promising design-independent alternative is dynamic voltage and accuracy scaling, whose adoption, however, is hindered by incompatibilities with standard design flows. In this paper, we propose a new methodology for the design of energy-quality scalable operators; our solution leverages runtime tuning of transistors threshold voltages to obtain a fine-grain control of the speed and power consumption of standard-cells within an operator. Thanks to the additional flexibility provided by this fine-grain knob, our method overcomes the main limitations of previous solutions, at the cost of a small area overhead. We demonstrate our approach on a 28 nm FDSOI technology; by exploiting the strong effect of back-gate biasing on threshold voltage, we achieve a power consumption reduction of more than 40% compared to the state-of-the-art, for the same precision.

Data Reuse Buffer Synthesis Using the Polyhedral Model

Current high-level synthesis (HLS) tools for the automatic design of computing hardware perform excellently for the synthesis of computation kernels, but they often do not optimize memory bandwidth. As accessing memory is a bottleneck in many algorithms, the performance of the generated circuit could benefit substantially from memory access optimization. In this paper, we present a method and a tool to automate the optimization of memory accesses to array data in HLS by introducing local memory tailored perfectly to store only the data that are used repeatedly. Our method detects data reuse in the source code of the algorithm to be implemented in hardware, selects and parameterizes data reuse buffers, and generates a register transfer level design of the data buffers and a matching loop controller that coordinates reuse buffers and datapath operations. Throughout this paper, the polyhedral representation is used extensively as it proves to be well suited for calculations on loop nests and data accesses. As a consequence, this paper is limited to affine programs which can be represented in this model. Experiments show that our method outperforms state-of-the-art academic and commercial HLS tools.

Design and Analysis of High Performance Ballistic Nanodevice-Based Sequential Circuits Using Monte Carlo and Verilog AMS Simulations

In this paper, we propose a design of traditional sequential circuits using high performance Ballistic Deflection Transistor (BDT). BDT technology was developed and experimentally proven to operate at Terahertz frequencies. Different structures of BDTs have been developed successfully to realize combinational logic functionality. Monte Carlo (MC) simulations have been extensively used to study these structures. By taking into account the effect of surface charges and dielectrics, we are able to correctly reproduce the non-linear I-V transfer characteristics, to predict scaling down behavior and to estimate the very high switching speed. We then used a three parameter Gaussian peak as a predictive model for the BDT and integrated it with Verilog AMS module to confirm the functionality of the designed circuits. Finally, we used a recently developed level-sensitive D-latch using two-BDTs structure, to explore traditional sequential circuits such as Shift Registers (SRs), Frequency Divider and Johnson Ring Counter, which play a pivotal role in many processing systems as common datapath operators. The simulation results have indicated the correct logic functionality of the implemented sequential circuits.

Design and Development of 8-Bits Fast Multiplier for Low Power Applications

Abstract —High speed multiplication has always been a fundamental requirement of high performance processors and systems. With MOS scaling and technological advances there is a need for design and development of high speed data path operators such as adders and multipliers to perform signal processing operations at very hi gh speed supporting higher data rates. In DSP applications, multiplication is one of the most utilized arithmetic operations as part of filters, convolves and transforms processors. Improving multipliers design directly benefits the high performance embedded processors used in consumer and industrial electronic products. Hence there is a need for design and development of high-speed architectures for N-bit multipliers supporting high speed and power. Here we review the architecture reported in the literature for multipliers and critical issues degrading the speed and power of these multiplier. Based on this review suitable modifications are suggested in the design for high speed and low power multipliers.

Power Optimization For A Datapath Of General Purpose Processor

This paper explores different data path architecture topologies for low power solutions. And we look at the energy optimization of different topologies. This paper is aimed at characterizing various architecture implementations of different data path operators like adders and multipliers and a different style of multiplier with minimum power and delay product and different adder topologies.

ILP models for simultaneous energy and transient power minimization during behavioral synthesis

In low-power design for battery-driven portable applications, the reduction of peak power, peak power differential, cycle difference power, average power and energy are equally important. These are different forms of dynamic power dissipation of a CMOS circuit, which is predominant compared to static power dissipation for higher switching activity. The peak power, the cycle difference power, and the peak power differential drive the transient characteristic of a CMOS circuit. In this article, we propose an ILP-based framework for the reduction of energy and transient power through datapath scheduling during behavioral synthesis. A new metric called “modified cycle power function” (CPF*) is defined that captures the above power characteristics and facilitates integer linear programming formulations. The ILP-based datapath scheduling schemes with CPF* as objective function are developed assuming three modes of datapath operation, such as, single supply voltage and single frequency (SVSF), multiple supply voltages and dynamic frequency clocking (MVDFC), and multiple supply voltages and multicycling (MVMC). We conducted experiments on selected high-level synthesis benchmark circuits for various resource constraints and estimated power, energy and energy delay product for each of them. Experimental results show that significant reductions in power, energy and energy delay product can be obtained.

Estimation of bit-level transition activity in data-paths based on word-level statistics and conditional entropy

Accurate models for the calculation of bit-level switching activity from word-level statistics are presented. The dual-bit type (DBT) model is combined with an entropy-based transition activity calculation. Assuming that the input signal of a DSP system is described by a random Gaussian process, the conditional entropy per bit is estimated by means of a novel sigmoidal model. An accurate polynomial approximation to the conditional entropy of the sign bits has been developed permitting the direct calculation of the switching activity. The propagation of signals through common data-path operators is studied. A triple-bit type (TBT) model is introduced to accurately describe the three activity regions of the multiplier output. Moreover, the proposed model is applied for the estimation of the switching activity at the nodes of a multiply–accumulate (MAC) architecture implementing a 24-tap FIR filter, for both synthetic and real data streams. The average error between measured and estimated values of the switching activity is less than 6% in all the cases encountered.

A word-level graph manipulation package

Verification has become one of the most important steps in circuit design. In this context, the verification of circuits described at the register-transfer level by means of hardware description languages (HDLs), like VHDL, becomes increasingly important. Decision diagrams (DDs) have proved successful for the representation of HDL expressions, like data-path operations or control logic. Unfortunately, there exists no graph type that can represent both word-level (i.e., data-path) and bit-level (control logic) functions with the same efficiency. Consequently, it is important to support multiple graph types in a graph manipulation package. This paper presents a word-level graph manipulation package [18] that provides a variety of different DDs and – even more important – enables operations between them. Furthermore, a complete set of data-path operations is given that can formally be verified based on word-level decision diagrams (WLDDs). The presented techniques allow a direct translation of HDL expressions to WLDDs. New algorithms for modulo and division on WLDDs are presented which turn out to be the core of the efficient verification procedures. The efficiency of the package is demonstrated by a large number of experiments. Finally, in a case study it is shown how the different package features interact and outperform conventional approaches.

A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis

This paper presents a partitioned and embedded BIST technique for data path like circuits. The BIST scheme is defined at behavioral level for full optimization of both system and BIST modes during High Level Synthesis. Test time, area overhead and fault coverage are under the scope of the method. User-given constraints on fault coverage to achieve on data path operators and on test time are used to guide the BIST insertion technique towards the lowest area overhead solution.

Eliminating false loops caused by sharing in control path

In high-level synthesis, resource sharing may result in a circuit containing false loops that create great difficulty in timing validation during the design sign-off phase. It is hence desirable to avoid generating any false loops in a synthesized circuit. Previous work [Stok 1992; Huang et al. 1995] considered mainly data path sharing for false loop elimination. However, for a complete circuit with both data path and control path, false loops can be created due to control logic sharing. In this article, we present a novel approach to detect and eleminate the false loops caused by control logic sharing. An effective filter is devised to reduce the computational complexity of false loop detection, which is based on checking the level numbers that are propagated from data path operators to imputs and outputs of the control path. Only the input/output pairs of the control path identified by the filter are further investigated by traversing into the data path for false loop detection. A removal algorithm is then applied to eliminate the detected false loops, followed by logic minimization to further optimize the circuit. Experimental results show that for the nine example circuits we tested, the final designs after false loop removal and logic minimization give only slightly larger area than the original ones that contain false loops.

High VelociTI processing [Texas Instruments VLIW DSP architecture

The Texas Instruments VelociTI architecture is a very long instruction word (VLIW) architecture. The TMS320C6x family of digital signal processors (DSPs) is the first to employ the VelociTI architecture, with the TMS3206201 (C6201) being the first device in this family. The C6201 is based on the fixed-point TMS320C62x (C62x) CPU. This article describes the VelociTI VLIW architecture and discusses the C62x, C67x, C6201, and the VelociTI development tools. An overview of the VelociTI including architectural principles, data path, instruction set, and pipeline operation is presented, and both the C62x fixed-point CPU and the C67x floating-point CPU are described. A summary of the C62x benchmark performance is also presented. The chip-level support outside the CPU that allows the C6201 to operate in a variety of high-performance DSP environments is also described. An overview of the C6x development environment is also given, demonstrating the breadth of the development environment and illustrating the programming methodology. The article concludes with a performance analysis of the C compiler.

An optimal clock period selection method based on slack minimization criteria

An important decision in synthesizing a hardware implementation from a behavioral description is selecting the clock period to schedule the datapath operations into control steps. Prior to scheduling, most existing behavioral synthesis systems either require the designer to specify the clock period explicitly or require that the delays of the operators used in the design be specified in multiples of the clock period. An unfavorable choice of clock period could result in operations being idle for a large portion of the clock period and, consequently, affect the performance of the synthesized design. In this article, we demonstrate the effect of clock slack on the performance of designs and present an algorithm to find a slack-minimal clock period. We prove the optimality of our method and apply it to several examples to demonstrate its effectiveness in maximizing design performance.

Design and implementation of the ‘Tiny RISC’ microprocessor

This paper describes the design and implementation of ‘Tiny RISC’, a 16-bit RISC-style microprocessor designed at UC Irvine. It was fabricated by MOSIS in a 2 μm n-well CMOS technology. Tiny RISC has been designed for optimized data path operation. A simple 32-bit extension of the data path results in a generic functional unit of a VLIW (very long instruction word) processor that is currently being developed at UC Irvine.