Data-driven Processor Research Articles

Super-Pipelined Implementation of IP Packet Classification

Abstract With developing all-optical communication networks, highly-functional and highspeed boundary routers and home gateways are becoming to be required. In this paper, high-speed pipelined algorithm for packet classification which is one of heavy load functions within boundary routers is proposed. Its software implementation scheme on a data-driven processor equipped with flexible capability of pipelined parallel processing is also discussed. Finally, it is shown at maximum performance exchanged for simulation and experimental hardware evaluation that the scheme achieves 12M IPv4 packets per second by only 6% additional hardware cost.

A self-timed superpipeline data-driven processor

With the advent of the ultimate integration era, the field of system configuration technology is in need of a novel paradigm to organically unify software with hardware and enable the realization of integrated systems. In the current study, the authors demonstrate that the “data-driven” concept has a very high potential as the basis for this unity, presenting concrete realization examples of self-timed superpipelines for a data-driven processor and examples of the corresponding software development environment. © 2000 Scripta Technica, Syst Comp Jpn, 31(8): 89–97, 2000

Implementation of TINA-based high-quality multimedia networks

Telecommunications Information Networking Architecture (TINA) is aiming at reusability and interoperability of software by use of location/fault transparency of objects based on distributed processing and object orientation technologies. Currently many attempts to realize TINA commercial systems are ongoing all over the world. As the first step of those attempts, the TINA Trial (TTT) is scheduled to be realized in 1998. To achieve the quality to be used for the commercial systems, quality study not only of software but also of hardware platforms becomes key. This paper intends to clarify the requirements of TINA-based high-quality multimedia networks and possible solutions by considering the TTT system which the authors are developing. The requirements from the perspective of quality are effective usage of system processing capability by effective multiprocessing without any processing overhead and improvement of system stability by fault management achieving autonomous system reconfiguration. This paper shows the desirability of applying stream-oriented data-driven processor to the TINA system so as to satisfy these requirements. © 1998 Scripta Technica. Electron Comm Jpn Pt 1, 81(8): 51–58, 1998

Data-driven architecture based on pipelined thread processing

A pure dynamic data-flow processor is capable of natural scheduling for parallel execution instructions in its architecture, and therefore we expect that it is applicable to fine-grain parallel computing. The data-driven processor Qv-x series is suitable for the ULSI design. It is made up of self-timed elastic transfer architectures. In this paper, we will report a new architecture Qth-0 to overcome the defects of overhead in generating packets and the total amount of hardware for the firing mechanism. In this Qth-0 architecture, we will provide the “pipelined thread processing mechanism.” Several instructions mutually depending on resources are gathered into a processing unit called a thread by static scheduling, and packets consisting of the thread and operand data are fed into the pipelined ALU. In horizontal VLIW, instructions independent of resources are multiprocessed in spatial shared form, but in the pipelined thread processing mechanism of this architecture, instructions which mutually depend on resources are multiprocessed in time shared form, so we consider this mechanism to be vertical VLIW. By adopting this mechanism, we could decrease the total number of transaction packets and increase the total number of instructions executed for matching token packets. As a result we could improve execution speed to between 9 and 40%. © 1998 Scripta Technica. Syst Comp Jpn, 28(13): 27–35, 1997

RD21: test of a silicon data-driven trigger processor

RD21 is a continuation of an R&D program to demonstrate the use of a planar silicon microvertex detector for triggering on the topology of heavy flavor events in a forward hadron-collider experiment. The RD21 project builds upon the successful P238 test of such a detector run very close to the circulating beams at the SPS-Collider. The specific goal of the RD21 project discussed here was to interface the P238 silicon system to a data-driven processor capable of performing complex calculations in real time and test the viability of the COBEX heavy-flavor topology trigger. We describe the processor and report on some results from a May 1994 test run.

The function processor: A data-driven processor array for irregular computations

The Function Processor is a data-driven processor array architecture, i.e. a regular structure of locally interconnected processing elements called Function Cells, which operate according to the data flow execution principle. By means of a compilation method developed for this architecture, data flow graphs for functional programs can be created and mapped onto the processor array, so that each Function Cell is assigned the execution of one graph node. The main result presented is a Function Cell architecture which has been designed to support the functionality required by these data flow graphs. We also give a brief description of a programming method for the architecture. Furthermore, some results from an implementation are presented.

The concept and implementation of data-driven processor arrays: I Koren (Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA), I Peled Computer (USA), vol. 20, no. 7, pp. 102–103 (July 1987)

The concept and implementation of data-driven processor arrays: I Koren (Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA), I Peled Computer (USA), vol. 20, no. 7, pp. 102–103 (July 1987)

The Concept and Implementation of Data-Driven Processor Arrays

The Concept and Implementation of Data-Driven Processor Arrays