Cylindrical Through-silicon Via Research Articles

Performance Analysis Using Air Gap Defected Through Silicon Via: Impact on Crosstalk and Power

In the recent past, various fabrication-related defects such as electromigration-induced open/short faults, interfacial cracks, and thermal stress-induced leakage problems in through silicon via (TSV) have a major impact on the reliability and performance of a TSV-based 3-D integrated circuit (IC). Considering these facts, this article for the first time provides the equivalent resistance-inductance-conductance-capacitance (RLGC) modeling and performance analysis of air gap-defected TSVs in comparison with defect free vertical interconnect at 7 nm technology in order to address reliability concerns. Considering different manufacturing imperfections such as air cracks and void holes, the analytical equations are derived using defective parameters to analyze the feasibility and reliability of defected TSVs. Using a driver-via-load (DVL) setup, an equivalent T-type electrical modeling of cylindrical TSV is proposed considering the impact of different forms of air-cracked defects. Therefore, the propagation delay, power dissipation, power delay product, peak noise, and dynamic crosstalk are analyzed using a carbon nanotube field effect transistor (CNTFET) driver. Encouragingly, considering a partial air-cracked TSV, the peak noise is improved by 4.83% approaching toward defect-free condition.

Design of EMI and suppression structure based on bar-via

Through-vias may radiate electromagnetic waves propagating in the substrate of 2.5D integration interposers under the excitation of high-frequency and high-speed signals carried by vias, thus inducing parasitic interference and edge radiation. In order to suppress electromagnetic interference (EMI) between through-silicon vias (TSV) on the silicon interposer, a 6G-B-TSV (Bar TSV) circular cage shield structure is proposed. Its shielding effect is superior to the unshielded structure and the traditional cylindrical TSV grounded shielding structure. In order to suppress EMI between the two cross-layer signal channels on the organic interposer, a 6G-B-Via shielding structure and a shielding fence structure consisting of single-row grounded B-Vias are proposed. Other, a design with B-Via fence on the edge of the substrate to suppress edge radiation is further proposed. The comparison of the simulation results shows the superiority of the design in shielding and suppression effect. Finally, the actual test results of samples verify the effectiveness of the structural designs and simulation schemes.

Role of Through Silicon Via in 3D Integration: Impact on Delay and Power

The metal–semiconductor (MES)-based through silicon vias (TSV) has provided attractive solutions over conventional metal–insulator–semiconductor (MIS) TSVs in recent three-dimensional (3D) integration. This paper aims a comprehensive performance analysis of MIS and MES structures considering different TSV shapes such as cylindrical, tapered, annular, and square. At 32[Formula: see text]nm technology, a CMOS-based coupled driver-via-load (DVL) setup is introduced wherein each via is represented an equivalent RLGC model of MIS- and MES-based TSV shapes. The proposed electrical model accurately considers the impact of micro bump and inter-metal dielectric (IMD) effects at 32[Formula: see text]nm technology as per the fabrication house. A 3D electromagnetic (EM) structural wave simulation is performed to validate the RLGC model parameters of different TSV structures for an operating frequency of up to 20[Formula: see text]GHz. The proposed DVL setup is used to analyze the propagation delay, power dissipation, and dynamic crosstalk for different MIS- and MES-based TSV shapes. A significant improvement in the cross-coupling behavior can be obtained using the MES-based tapered TSV compared to the other MIS structures. Additionally, the power delay product (PDP) of the tapered MES is reduced by 92.4% compared to the conventional MIS-based cylindrical TSV.

Miniaturized SIW Bandpass Filter Based on TSV Technology for THz Applications

A miniaturized substrate integrated waveguide bandpass filter with an area of 0.682 × 0.210 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> is proposed based on through-silicon via (TSV) technology for terahertz (THz) applications. The design method of the THz cavity filter based on rectangular TSV is introduced and the filtering characteristics are investigated by the finite element method and the mode matching method. The rectangular TSV is substituted by cylindrical structures and the THz cavity filter is fabricated and measured in order to investigate the possibility of integration with typical three-dimensional integrated circuit manufacturing processes. The cavity filter utilizing cylindrical TSV exhibits a bandwidth of 0.051 THz centered at 0.331 THz, an insertion loss of 1.5 dB, and a reflection of higher than 15 dB in the passband.

Effect of cooling fluids on high frequency electric and magnetic fields in microelectronic systems with integrated TSVs

A fully 3D conjugate numerical analysis was performed to reveal the effects of air, R134a refrigerant and water on electromagnetic fields of electronic cooling designs made of arrays of micro pin-fins with integrated Through-Silicon-Vias (TSVs). The integrated TSV cooling configuration included 8 cylindrical TSVs with 150µm diameter each and 200µm height. The external dimensions of the silicon substrate were 900×700×280µm. Each TSV encapsulated four equally spaced copper vias each having a diameter of 40µm. The impacts of the presence of the stationary cooling fluids without heat transfer on TSVs electric and magnetic fields were examined for five different frequencies; 100MHz, 500MHz, 1GHz, 5GHz and 10GHz. Then, separately, the effects of moving cooling water with temperature-dependent physical properties were studied while exposing the cooled micro pin-fin array to a uniform heat flux of 500Wcm−2. For the case of stagnant and moving cooling fluids it was found that water influences the electric field twice as much as either R134a or air and that this influence decreases only negligibly with the increase in frequency of the electric current passing through the TSVs. The influence of the presence of the stagnant and moving cooling fluids on the magnetic field is orders of magnitude smaller and reduces rapidly with the increased frequency.

Extreme fast filling of conical shape through-silicon vias in 3 minutes and additive optimization

Through-silicon via (TSV) technology has been quickly improved, however, there are challenges in reducing electrodeposition time. In this research, new conical TSVs, 3μm diameter and 27μm depth (3×27μm), were made. The flow pattern of the electrolyte inside a conical TSV and a cylindrical TSV is simulated with a TSV chip attached on a rotating disk electrode (RDE) rotating at 1000rpm in the electrolyte. The flow pattern inside conical TSVs confirmed advantages of the conical shape over the cylindrical shape. The conical shape forms deeper vortexes and shows higher velocities at the same depth than the cylindrical shape. A character of electrolyte bases on anodic area charge was used to optimize electrolyte bath composition for the extreme fast filling. Without additives, the anodic area charge at 1000rpm was larger than that at 10rpm, however, the reverse obtained in the presence of additives. D-optimal designs for quantitative multilevel of additives were applied to create an experiment plan. The result confirmed a strong effect of Cl− concentration and interactions of Cl− with polyethylene glycol (PEG) and bis-(3-sodiumsulfopropyl)-disulfide (SPS) with sulfonated diallyl dimethyl ammonium chloride copolymer (SDDACC) which bring to anodic area charge at 1000rpm was smaller than that at 10rpm. In an optimal concentration of SDDACC, the 3×27μm conical TSV was filled within 3minutes. A new additive acceleration mechanism was proposed from the accumulation of Cu(I) thiolate inside vortexes.

Modeling and Layout Optimization for Tapered TSVs

Through-silicon-via (TSV) offers vertical connections for 3-D ICs. Due to its large dimensions and nonideal etching process, TSVs layout needs to be carefully optimized to balance peak current density and delay for digital circuit. This brief investigates the TSVs tapering effect (which is an inevitable byproduct of deep reactive Ion etching-based manufacturing) and its impact on the TSVs electrical properties. We show that the current crowding effect is more severe in realistic tapered TSVs than ideal cylindrical TSVs. We propose a nonuniform current density model for tapered TSVs, which achieves considerable accuracy and speedup in estimating the current density distribution, when compared with the existing models developed for cylindrical TSVs. We apply our model to perform a detailed study on: 1) impact of TSVs tapering on peak current density and 2) wire sizing problem to minimize TSV-involved path delay under second-order delay model while keeping the peak current density within tolerable levels. A new dynamic programming-based heuristic is proposed to find the optimal wire configuration, which reduces both peak current density and delay, thereby improving the reliability and performance.

An efficient method for comprehensive modeling and parasitic extraction of cylindrical through-silicon vias in 3D ICs**Project supported by the National Natural Science Foundation of China (No. 61422402), and the Tsinghua University Initiative Scientific Research Program.

To build an accurate electric model for through-silicon vias (TSVs) in 3D integrated circuits (ICs), a resistance and capacitance (RC) circuit model and related efficient extraction technique are proposed. The circuit model takes both semiconductor and electrostatic effects into account, and is valid for low and medium signal frequencies. The electrostatic capacitances are extracted with a floating random walk based algorithm, and are then combined with the voltage-dependent semiconductor capacitances to form the equivalent circuit. Compared with the method used in Synopsys's Sdevice, which completely simulates the electro/semiconductor effects, the proposed method is more efficient and is able to handle the general TSV layout as well. For several TSV structures, the experimental results validate the accuracy of the proposed method for the frequency range from 10 kHz to 1 GHz. The proposed method demonstrated 47× speedup over the Sdevice for the largest 9-TSV case.

3D ICs-power Analysis Using Cylindrical and Co-axial Through Silicon Via (TSV)

In this study, analytical model and electrical equivalent circuit of Through Silicon Via (TSV) is analyzed. Through silicon Vias form an integral component of the 3-D IC technology by enabling vertical interconnections in 3-D ICs. Among various types, the performances of the simplified lumped TSV model of cylindrical and co-axial type were studied. The performance analyses of these structures were presented by introducing these structures between the tiers of digital circuits. The power consumption of the transistor level digital circuits for single tier without TSV and multiple tiers with cylindrical TSV and Co-axial TSV was simulated using Virtuoso Schematic Editor of Cadence. The comparison for cylindrical and co-axial TSV model with different level tiers were tabulated and performed.

Effects of Copper Plasticity on the Induction of Stress in Silicon from Copper Through-Silicon Vias (TSVs) for 3D Integrated Circuits

Finite element modeling (FEM) has been undertaken to characterize the effect of copper (Cu) elasto-plastic behavior on the induction of stress in 3D crystalline silicon (Si) systems incorporating Cu through-silicon vias (TSVs). Using a linear isotropic hardening model, simulations of thermal annealing cycles in Cu TSVs indicate that, for sufficient anneal temperatures, plastic yield within the Cu leads to substantial residual stress in the neighboring Si following cool-down. Simulated Si stress profiles of annealed isolated TSVs agreed with experimental Raman microscopy measurements of post-anneal stress profiles in Si near isolated 5?×?25 μm cylindrical TSVs on a 300 mm Si wafer. Simulations were expanded to investigate the impact of Cu plasticity (yield stress and tangent modulus) on the residual stress profile in Si near isolated TSVs and linear TSV arrays. The results show that the magnitude and extent of the TSV-induced stress field in Si is a non-monotonic function of Cu yield stress. Moreover, the tensile or compressive nature of TSV-induced stress within and outside linear TSV arrays is also a strong function of the Cu yield stress. The simulated impact of Cu tangent modulus on TSV-induced stress in Si is less substantial. The implications of these results for TSV layout with respect to active device placement in a 3D system are discussed.