Custom Application Specific Integrated Circuit Research Articles

Custom ASIC Design for SHA-256 Using Open-Source Tools

The growth of digital communications has driven the development of numerous cryptographic methods for secure data transfer and storage. The SHA-256 algorithm is a cryptographic hash function widely used for validating data authenticity, identity, and integrity. The inherent SHA-256 computational overhead has motivated the search for more efficient hardware solutions, such as application-specific integrated circuits (ASICs). This work presents a custom ASIC hardware accelerator for the SHA-256 algorithm entirely created using open-source electronic design automation tools. The integrated circuit was synthesized using SkyWater SKY130 130 nm process technology through the OpenLANE automated workflow. The proposed final design is compatible with 32-bit microcontrollers, has a total area of 104,585 µm2, and operates at a maximum clock frequency of 97.9 MHz. Several optimization configurations were tested and analyzed during the synthesis phase to enhance the performance of the final design.

Highly Miniaturized, Low-Power CMOS ASIC Chip for Long-Term Continuous Glucose Monitoring.

The objective of this work is to develop a highly miniaturized, low-power, biosensing platform for continuous glucose monitoring (CGM). This platform is based on an application-specific integrated circuit (ASIC) chip that interfaces with an amperometric glucose-sensing element. To reduce both size and power requirements, this custom ASIC chip was implemented using 65-nm complementary metal oxide semiconductor (CMOS) technology node. Interfacing this chip to a frequency-counting microprocessor with storage capabilities, a miniaturized transcutaneous CGM system can be constructed for small laboratory animals, with long battery life. A 0.45 mm × 1.12 mm custom ASIC chip was first designed and implemented using the Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS technology node. This ASIC chip was then interfaced with a multi-layer amperometric glucose-sensing element and a frequency-counting microprocessor with storage capabilities. Variation in glucose levels generates a linear increase in frequency response of this ASIC chip. In vivo experiments were conducted in healthy Sprague Dawley rats. This highly miniaturized, 65-nm custom ASIC chip has an overall power consumption of circa 36 µW. In vitro testing shows that this ASIC chip produces a linear (R2 = 99.5) frequency response to varying glucose levels (from 2 to 25 mM), with a sensitivity of 1278 Hz/mM. In vivo testing in unrestrained healthy rats demonstrated long-term CGM (six days/per charge) with rapid glucose response to glycemic variations induced by isoflurane anesthesia and tail vein injection. The miniature footprint of the biosensor platform, together with its low-power consumption, renders this CMOS ASIC chip a versatile platform for a variety of highly miniaturized devices, intended to improve the quality of life of patients with type 1 and type 2 diabetes.

Toward the Realization of a Programmable Metasurface Absorber Enabled by Custom Integrated Circuit Technology

The realization of a programmable metasurface, enabled by a custom application-specific integrated circuit (ASIC), is presented in this paper. The ASIC is used to provide an adaptive complex impedance load to each of the metasurface unit cells. Various technology nodes are analyzed for the implementation of tunable complex impedance loading elements before one is selected for the final implementation, in which four complex loads are placed within each integrated circuit, and each load is controlled by two digital-to-analog converters. Furthermore, the ASICs populate the back of the metasurface to form a mesh network to enable programmability. The paper includes practical limitations that affect the realization, as well as an example adaptive metasurface absorber that builds upon the practical tuning range of the ASIC. Perfect absorption for both transverse electric and transverse magnetic polarization is demonstrated.

Design and Testing of the Address in Real-Time Data Driver Card for the Micromegas Detector of the ATLAS New Small Wheel Upgrade

The address in real-time data driver card (ADDC) is designed to transmit the trigger data in the micromesh gaseous structure (Micromegas, MM) detector of the ATLAS new small wheel (NSW) upgrade. The address in real-time (ART) signals are generated by the front-end application-specific integrated circuit (ASIC), named VMM chip, to indicate the address of the first above-threshold event. A custom ASIC (ART ASIC) is designed to receive the ART signals from the VMM chip and implement the hit selection. The processed data from the ART ASIC will be transmitted out of the NSW through the gigabit transceiver (GBTx) serializer, the unidirectional versatile twin transmitter (VTTx), and fiber-optic links. The ART signal is critical for the ATLAS experiment trigger selection; thus, the performance and stability of the ADDC is very important. To ensure extensive testing of the ADDC, a field-programmable gate array (FPGA) mezzanine card (FMC)-based testing platform and a specially designed firmware/software are developed. This test platform works with the commercial Xilinx VC707 FPGA development kit; independent of the other electronics in the NSW, it can test all the functions of the ADDC and it has long-term stability. This article will introduce the design, testing procedure, and results of the ADDC and the FMC testing platform.

A pulse oximeter system, OxiSense, with embedded signal processing using an ultra-low power ASIC designed for testability

This paper presents a complete IoT enabled pulse oximeter (PO) system, called OxiSense, made using a custom designed low power application specific integrated circuit (ASIC) for signal conditioning. One of the novel aspects of the developed system is the testability of all the important modules of the ASIC (both analog and digital) using auxiliary circuits implemented in the ASIC. Another novel aspect is a new embedded and efficient signal processing algorithm which is robust to small motion artifacts. This new algorithm has been implemented on a low-power micro-controller (embedded processing mode) as well as on PC using Python (remote processing mode). The PO ASIC is fabricated in 180 nm mixed-mode CMOS technology and it works at 1.8 V supply voltage. The average power consumption of the analog front-end is 176 µW and that of the digital module controlling the analog front-end is 23 µW. The prototype PO system made using the custom ASIC operates from a 3.7 V lithium ion battery and consumes about 8 mW power. The prototype is housed in a 3D printed casing and it connects with a display device via USB or wirelessly to laptop/smartphone/tablet. Readings on 20 subjects, both in the lab and in hospital, show less than 2% deviation in the measured SpO2 level and worst case deviation of 2.7 beats per minute for the measured heart rate, when compared with the commercial POs.

A Low-Cost Time-Correlated Single Photon Counting System for Multiview Time-Domain Diffuse Optical Tomography

Diffuse optical tomography resorting to time-domain measurements (TD-DOT) provides information-rich data that have not yet been fully exploited for image reconstruction, notably to increase imaging spatial resolution. Current TD-DOT scanners suffer from a very low sensitivity owing to their small number of detection channels. This leads to excessively long acquisition times for in vivo imaging. To obtain a higher number of detection channels, thus increasing detection density, a low-cost time-correlated single photon counting (TCSPC) system dedicated to TD-DOT was designed, resorting solely to off-the-shelf electronic components to reduce costs, in distinction to custom application-specific integrated circuit solutions. The system features four input channels, each of them including a leading-edge discriminator for direct interfacing with off-the-shelf photodetector modules and a programmable delay line to compensate for undesired propagation delays, thus also avoiding manual adjustment of cable lengths. The system supports a large number of TCSPC channels using a daisy-chain configuration through an onboard Ethernet switch. It also features a 13.02 ps bin width with a 12.5 ns dynamic range. Results show excellent linearity, with a $\sigma _{\mathrm{ DNL}}$ of 1.7% least significant bit (LSB), peak differential nonlinearity of 5% LSB, and peak integral nonlinearity of 10% LSB and an average accuracy of 19 ps full-width at half-maximum (FWHM) throughout two separate four-channel systems. The system was tested in a TD-DOT acquisition setup, and 37 ps FWHM instrument response functions were obtained using a single-photon avalanche diode (SPAD) detector. Diffuse intrinsic measurements were also acquired and compared with a reference TCSPC system showing similar results.

Single-Objective Path Planning for Autonomous Robots Using Reconfigurable Analog VLSI

This paper presents path planning using reconfigurable analog very large scale integrated (AVLSI) circuits. Existing research has shown that custom AVLSI circuits known as application specific integrated circuits (ASICs) can theoretically be used for path planning. There are two main drawbacks to using custom ASICs: 1) circuit designs are fixed to some extent (not changeable) and 2) long design cycle/fabrication time (order of months). Reconfigurable analog circuits called field-programmable analog arrays (FPAAs) have been used to implement a variety of AVLSI circuits in a short time (order of minutes). This paper presents an algorithm for mapping a robot’s environment onto an FPAA, and then presents hardware results using an FPAA to implement the path-planning algorithm. Experimental results and analysis are presented for 24 environment scenarios. Digital search methods like breadth-first search have solutions which scale on the order of $\boldsymbol {O( {4^{d}} )}$ whereas this paper will show our analog solution is on the order of $\boldsymbol {O( d )}$ where ${d}$ is the depth of the solution.

A Coprocessor for the Fast Tracker Simulation

The Fast Tracker (FTK) executes real-time tracking for online event selection in the ATLAS experiment. Data processing speed is achieved by exploiting pipelining and parallel processing. Track reconstruction is executed in two stages. The first stage, implemented on custom application-specific integrated circuit (ASICs) called associative memory (AM) chips, performs pattern matching (PM) to identify track candidates in low resolution. The second stage, implemented on field programmable gate arrays (FPGAs), builds on the PM results, performing track fitting in full resolution. The use of such a parallelized architecture for real-time event selection opens up a new, huge computing problem related to the analysis of the acquired samples. Millions of events have to be simulated to determine the efficiency and the properties of the reconstructed tracks with a small statistical error. The AM chip emulation is a computationally intensive task when implemented in software running on commercial resources. This paper proposes the use of a hardware coprocessor to solve this problem efficiently. We report on the implementation and performance of all the functions requiring massive computing power in a modern, compact embedded system for track reconstruction. That system is the miniaturization of the complex FTK processing unit, which is also well suited for powering applications outside the realm of high energy physics.

Efficient Hardware Architecture for Integer Implementation of Multi-Alphabet Arithmetic Coding for Data Mining

The aim of this paper is to create an efficient hardware architecture for the multi-alphabet arithmetic coding (MA-AC) in semicustom and full custom application specific integrated circuit (ASIC). Generally, hardware realisation of MA-AC involves numerical processing and entropy coding, which employ the floating point (FP) arithmetic which is replaced by integer implementation in such a way that the symbol counts are used instead of probabilities. Novel hardware architecture is designed by modifying the update equations for upper and lower limits of multi-alphabet arithmetic encoder and decoder based on the update equation of the FP implementation. The proposed hardware architectures are synthesised in Xilinx and Altera Field Programmable Gate Array (FPGA) devices to evaluate resource utilisation and speed. Also, the physical design is encountered as ASIC device using Cadence Design environment tsmc 0.18 µm technology which shows area reduction of 12.75% and 23.61% and power consumption of 29.86% and 38.89% for encoder and decoder, respectively.

Ex Vivo HIFU Experiments Using a $32 \times 32$ -Element CMUT Array.

High-intensity focused ultrasound (HIFU) has been used as noninvasive treatment for various diseases. For these therapeutic applications, capacitive micromachined ultrasonic transducers (CMUTs) have advantages that make them potentially preferred transducers over traditional piezoelectric transducers. In this paper, we present the design and the fabrication process of an 8 ×8 -mm 2 32 ×32 -element 2-D CMUT array for HIFU applications. To reduce the system complexity for addressing the 1024 transducer elements, we propose to group the CMUT array elements into eight HIFU channels based on the phase delay from the CMUT element to the targeted focal point. Designed to focus at an 8-mm depth with a 5-MHz exciting frequency, this grouping scheme was realized using a custom application-specific integrated circuit. With a 40-V dc bias and a 60-V peak-to-peak ac excitation, the surface pressure was measured 1.2 MPa peak-to-peak and stayed stable for a long enough time to create a lesion. With this dc and ac voltage combination, the measured peak-to-peak output pressure at the focus was 8.5 MPa, which is expected to generate a lesion in a minute according to the temperature simulation. The following ex vivo tissue experiments successfully demonstrated its capability to make lesions in both bovine muscle and liver tissue.

Radiation testing campaign results for understanding the suitability of FPGAs in detector electronics

SRAM based Field Programmable Gate Arrays (FPGAs) have been rarely used in High Energy Physics (HEP) due to their sensitivity to radiation. The last generation of commercial FPGAs based on 28nm feature size and on Silicon On Insulator (SOI) technologies are more tolerant to radiation to the level that their use in front-end electronics is now feasible. FPGAs provide re-programmability, high-speed computation and fast data transmission through the embedded serial transceivers. They could replace custom application specific integrated circuits in front end electronics in locations with moderate radiation field. The use of a FPGA in HEP experiments is only limited by our ability to mitigate single event effects induced by the high energy hadrons present in the radiation field.

A Geometric Algebra Co-Processor for Color Edge Detection

This paper describes advancement in color edge detection, using a dedicated Geometric Algebra (GA) co-processor implemented on an Application Specific Integrated Circuit (ASIC). GA provides a rich set of geometric operations, giving the advantage that many signal and image processing operations become straightforward and the algorithms intuitive to design. The use of GA allows images to be represented with the three R, G, B color channels defined as a single entity, rather than separate quantities. A novel custom ASIC is proposed and fabricated that directly targets GA operations and results in significant performance improvement for color edge detection. Use of the hardware described in this paper also shows that the convolution operation with the rotor masks within GA belongs to a class of linear vector filters and can be applied to image or speech signals. The contribution of the proposed approach has been demonstrated by implementing three different types of edge detection schemes on the proposed hardware. The overall performance gains using the proposed GA Co-Processor over existing software approaches are more than 3.2× faster than GAIGEN and more than 2800× faster than GABLE. The performance of the fabricated GA co-processor is approximately an order of magnitude faster than previously published results for hardware implementations.

Accelerated-stress reliability evaluation for an encapsulated wireless cortical stimulator.

In preparing a wireless cortical stimulator for use in the Intracortical Visual Prosthesis (ICVP) project at the Illinois Institute of Technology (IIT), an accelerated environmental stress test is being performed on prototype stimulator modules. Stimulator devices, containing a custom application specific integrated circuit (ASIC), and encapsulated with PDMS, were soaked in an autoclave chamber at 121°C and 100% relative humidity for more than 2200 hours with and without power supplied to the ASIC. Experimental results showed no physical degradation of the stimulator devices after soaking. Reverse telemetry that measures the stimulator internal power supply, recorded periodically over the entire test time, verified that the devices were electrically functioning, as designed, without deterioration. Taking into consideration other standard reliability test environments, the accelerated moisture resistance-biased autoclave testing duration of 2200 hours, as conducted in this study, overwhelms other less-severe test conditions and demonstrates long term stability of the proposed vision prosthesis device with proven thermo-mechanical and electrical robustness.

Design and Implementation of a Preprocessing Circuit for Bandpass Signals Acquisition

The processing capabilities that are included into the acquisition block of the real-time digital oscilloscopes largely contribute to determine the overall performance of the instrument. Their remarkable improvement has made it possible to enhance the performance in terms of increased measurement rate, automation, and reduced measurement uncertainty related to quantization and noise. This paper presents the implementation of a preprocessing circuit for a novel acquisition mode of bandpass signals, which is characterized by an increased vertical resolution. Although the theoretical foundations were recently presented with simulative results, here, the circuital implementation of such an acquisition mode is presented. The focus is on mid or low cost digital oscilloscopes that can improve their vertical resolution at a negligible additional cost. First, a preliminary field programmable gate array implementation is considered to evaluate the achievable performance both from a theoretical point of view and throughout experimental tests. Then, a custom application specific integrated circuit implementation, in 28-nm complementary metal-oxide-semiconductor technology is analyzed. Along with the parameter optimization, the work experimentally tests the acquisition mode and evaluates the effects of nonideal characteristics such as finite word length and nonideal filtering. The increase in the effective number of bit (ENoB) is up to 2.5 bit, whereas the ENoB degradation because of word length and nonideal filtering is quantified as ~ 1.1 and 0.5 bit. The design highlights that there is substantial margin for parallel implementation that is the base to candidate the proposed solution as a remarkable option for the next generation oscilloscopes.

A 200 °C Motor Control ASIC

A custom application-specific integrated circuit (ASIC) has been designed for positional control of brushless DC or servo motors in high-temperature (>200 °C) environments. Applications would include valve and position control for aerospace and industrial systems. Patented high-temperature circuit design techniques facilitate hightemperature operation from a conventional, low-cost, 0.5-micron bulk CMOS foundry process. The ASIC is highly integrated to enable software- and processor-free local control of motor position, and uses external power MOSFETs for motor commutation. Motor position can be controlled in open- or closed-loop modes with an integrated rotational variable displacement transformer (RVDT) direct digital synthesis (DDS) waveform generator, rail-to-rail op-amp driver and demodulation circuit. The ASIC can accept both analog (0–10 V) or digital (SPI bus) position setpoint commands from an external controller. Motor position is indicated by both analog and digital output signals. The full-scale displacement of the controlled motor is programmable from 5 to 8 bits of resolution, permitting 32–256 positions of control. Safety features such as a 500-ms power-on delay, overtemperature and motor overcurrent detection, and control signal undervoltage lockout were included to minimize the need for external control. ASIC bench-test results confirmed circuit functionality at ambient temperatures up to 225 °C using room-temperature power MOSFETs and motor load. ASIC performance at the 8-bit level was demonstrated, although the clock oscillator frequency shifted by about 15% over the full temperature range. Control of the motor at 200 °C was also demonstrated, although moderate loss of motor holding torque was observed due to internal heat generation in the motor. The ASIC was combined with commercially-available off-the-shelf high-temperature components on a printed wiring board (PWB) to form a compact (4 × 3.5 inch) motor control demonstration system capable of prolonged operation at temperatures beyond 200 °C. Environmental and long-term testing of the PWB is planned to demonstrate system reliability.

A time digitizer for space instrumentation using a field programmable gate array

Space instruments such as time-of-flight (TOF) mass spectrometers and altimeters rely on time-to-digital converters (TDCs) to measure accurately times in the picosecond to microsecond range. Time-to-digital conversion is often implemented with analog circuitry or more recently with custom ASIC (Application Specific Integrated Circuit) devices. The analog approach may be costly in terms of circuit board area and parts count, while ASIC development is risky and costly when system requirements may change. Here, we present a highly flexible, accurate, and low-cost field-programmable gate array (FPGA) implementation of such TDC functionality. Compared with other technologies, this method reduces the parts count in TOF-supporting circuits and provides design flexibility in TOF instrumentation, especially for use in space or for applications with a number of sensors too small to warrant the development of a dedicated ASIC. Our technique can accommodate one or more STOP pulse measurements for each START pulse as signal reference, effectively providing measurements of multiple times-of-flight with the same start trigger. Alternatively, all pulse event edges can receive an absolute time stamp, enabling a broad set of new sensor applications. This novel design is based on the construction of a delay-line internal to the FPGA. Propagation variations due to temperature and supply voltage, which typically limit FPGA-based timing designs, are automatically compensated, allowing active signal processing 100% of the time. A methodology for the characterization of internal delay-line timing and nonlinearity has also been developed and is not specific to a particular FPGA architecture. We describe the design of this FPGA-based TDC and also describe detailed tests with a Xilinx XC2V1000. For single non-repetitive events, this design achieves 60 ps accuracy (standard deviation of error); a simplified implementation is suitable for non-reprogrammable FPGAs.

An implantable wireless neural interface for recording cortical circuit dynamics in moving primates

Objective. Neural interface technology suitable for clinical translation has the potential to significantly impact the lives of amputees, spinal cord injury victims and those living with severe neuromotor disease. Such systems must be chronically safe, durable and effective. Approach. We have designed and implemented a neural interface microsystem, housed in a compact, subcutaneous and hermetically sealed titanium enclosure. The implanted device interfaces the brain with a 510k-approved, 100-element silicon-based microelectrode array via a custom hermetic feedthrough design. Full spectrum neural signals were amplified (0.1 Hz to 7.8 kHz, 200× gain) and multiplexed by a custom application specific integrated circuit, digitized and then packaged for transmission. The neural data (24 Mbps) were transmitted by a wireless data link carried on a frequency-shift-key-modulated signal at 3.2 and 3.8 GHz to a receiver 1 m away by design as a point-to-point communication link for human clinical use. The system was powered by an embedded medical grade rechargeable Li-ion battery for 7 h continuous operation between recharge via an inductive transcutaneous wireless power link at 2 MHz. Main results. Device verification and early validation were performed in both swine and non-human primate freely-moving animal models and showed that the wireless implant was electrically stable, effective in capturing and delivering broadband neural data, and safe for over one year of testing. In addition, we have used the multichannel data from these mobile animal models to demonstrate the ability to decode neural population dynamics associated with motor activity. Significance. We have developed an implanted wireless broadband neural recording device evaluated in non-human primate and swine. The use of this new implantable neural interface technology can provide insight into how to advance human neuroprostheses beyond the present early clinical trials. Further, such tools enable mobile patient use, have the potential for wider diagnosis of neurological conditions and will advance brain research.

Focusing on Size and Energy Dependence of Electron Microbursts From the Van Allen Radiation Belts

Focusing on Size and Energy Dependence of Electron Microbursts From the Van Allen Radiation Belts

Low-Power Wireless Micromanometer System for Acute and Chronic Bladder-Pressure Monitoring

This letter describes the design, fabrication, and testing of a wireless bladder-pressure-sensing system for chronic, point-of-care applications, such as urodynamics or closed-loop neuromodulation. The system consists of a miniature implantable device and an external RF receiver and wireless battery charger. The implant is small enough to be cystoscopically implanted within the bladder wall, where it is securely held and shielded from the urine stream. The implant consists of a custom application-specific integrated circuit (ASIC), a pressure transducer, a rechargeable battery, and wireless telemetry and recharging antennas. The ASIC includes instrumentation, wireless transmission, and power-management circuitry, and on an average draws less than 9 μA from the 3.6-V battery. The battery charge can be wirelessly replenished with daily 6-h recharge periods that can occur during the periods of sleep. Acute in vivo evaluation of the pressure-sensing system in canine models has demonstrated that the system can accurately capture lumen pressure from a submucosal implant location.

Programmable Neural Processing on a Smartdust for Brain-Computer Interfaces

Brain-computer interfaces (BCIs) offer tremendous promise for improving the quality of life for disabled individuals. BCIs use spike sorting to identify the source of each neural firing. To date, spike sorting has been performed by either using off-chip analysis, which requires a wired connection penetrating the skull to a bulky external power/processing unit, or via custom application-specific integrated circuits that lack the programmability to perform different algorithms and upgrades. In this research, we propose and test the feasibility of performing on-chip, real-time spike sorting on a programmable smartdust, including feature extraction, classification, compression, and wireless transmission. A detailed power/performance tradeoff analysis using DVFS is presented. Our experimental results show that the execution time and power density meet the requirements to perform real-time spike sorting and wireless transmission on a single neural channel.