Current-starved Voltage-controlled Oscillator Research Articles

Design and analysis of 7-stage MOS current mode logic power gated MOSFETs in current starved voltage-controlled oscillator for the phase locked loop application

This paper presents a new process, voltage and temperature (PVT) tolerant 7-stage ring type current starved voltage-controlled oscillator (CS-VCO). In this, a 7-stage ring VCO is proposed using power gated technique for phase locked loop (PLL) application. PLL plays a major role in clock and data recovery, Global Positioning System (GPS) system and satellite communications. For the high-speed application of PLL it is designed using 7-stage inverter delay cell with MOS current mode logic (MCML) technique. The circuit undergoes process, voltage and temperature variations with different parameters such as average power, oscillation frequency, phase noise, tuning range and output noise. The Monte-Carlo analysis justifies the proposed design provides better results. The circuit is simulated under 45 nm CMOS technology using cadence virtuoso. The average power consumption of the proposed circuit is 29.368 µW with the oscillation frequency of 3.06 GHz. The output noise and the phase noise of the proposed VCO are -161.55 dB and -125.92 dBc/Hz respectively. It achieves the frequency tuning range (FTR) of 95.09%. The obtained simulation results are highly robust with PVT making the circuit suitable for PLL application.

An Intelligent Sensing Framework for Post-Manufacturing Performance Measurement and Healing of CSVCO

With CMOS technology scaling for miniaturization and performance improvement, analog and radio frequency integrated circuits (RFICs) are very much affected by process variations leading to performance degradation. A post-manufacturing healing mechanism with low overhead is desirable to compensate for these variations. A machine learning (ML)-assisted sensing mechanism has been proposed in this work for design of nonintrusive process variation sensor (PVS). Low-cost test signatures (TSs) extracted from these PVS are placed close to the circuit under test (CUT) and this does not load or couple to any nodes of CUT. As the TSs remain invariant with the shifts in control knobs (CKs), performance healing against process variations can be achieved with a single set of extracted TSs. A novel one-step healing approach is proposed in this work for selection of appropriate CK with the help of a neural regression model during the production test in automated test equipment (ATE). The proposed healing approach is illustrated on a current-starved voltage-controlled oscillator (CSVCO) circuit, to recover yield loss due to fabrication process variations.

Performance Analysis of Ring Oscillators and Current-Starved VCO in 45-nm CMOS Technology

Abstract: This paper presents a relative study among two Ring oscillators architecture (CMOS, NMOS) and current-starved Voltage-controlled oscillator (CS-VCO) on the basis of different parameters like power dissipation ,phase noise etc. All the design has been done in 45- nm CMOS technology node and 2.3 GHz Centre frequency have been taken for the comparison because of their applications in AV Devices and Radio control. An inherent idea of the given performance parameters has been realize by thecomparative study. The comparative data shows that NMOS based Ring oscillator is good option in terms of the phase noise performance. In this study NMOS Ring Oscillator have attain a phase noise -97.94 dBc/Hz at 1 MHz offset frequency from 2.3 GHz center frequency. The related data also shows that CMOS Ring oscillator is the best option in terms of power consumption. In this work CMOS Ring oscillator evacuatea power of 1.73 mW which is quite low. Keywords: Voltage controlled oscillator (VCO), phase noise, power consumption, Complementary metal-oxide-semiconductor (CMOS), Current Starved Voltage-Controlled Oscillator (CS- VCO), Pull up network (PUN), Pull down network (PDN)

Proposed 3.5 µW CNTFET-MOSFET hybrid CSVCO for power-efficient gigahertz applications

PurposeSeveral ultra-low power and gigahertz current-starved voltage-controlled oscillator (CSVCO) circuits have been proposed and compared here. The presented structures are based on the three-stage hybrid circuit of the carbon nanotube field-effect transistors (CNTFETs) and low-power MOSFETs. The topologies exploit modified and compensated Schmitt trigger comparator parts to demonstrate better consumption power and frequency characteristics. The basic idea in the presented topologies is to compensate the Schmitt trigger comparator part of the basic CSVCO for achieving faster carrier mobility of the holes, reducing transistor leakage current and eliminating dummy transistors.Design/methodology/approachThis study aims to propose and compare three different comparator-based VCOs that have been implemented using the CNTFETs. The considered circuits are shown to be capable of delivering the maximum 35 tuning frequency in the order of 1 GHz to 5 GHz. A major power thirsty part of the high-frequency ring VCOs is the Schmitt trigger stage. Here, several fast and low-power Schmitt trigger topologies are exploited to mitigate the dissipation power and enhance the oscillation frequency.FindingsAs a result of proposed modifications, more than one order of magnitude mitigation in the VCO power consumption with respect to the previously presented three-stage CSVCO is reported here. Thus, a VCO dissipation power of 3.5 µW at the frequency of 1.1 GHz and the tuning range of 26 per cent is observed for the well-established 32 nm technology and the supply voltage of 1 V. Such a low dissipation power is obtained around the operating frequency of the battery-powered cellular phones. In addition, using the p-carrier mobility compensation and enhancing the rise time of the Schmitt trigger part of the CSVCO, a maximum of 2.38 times higher oscillation frequency and 72 per cent wider tuning range with respect to Rahane and Kureshi (2017) are observed. Simultaneously, this topology exhibits an average of 20 per cent reduction in the power consumption.Originality/valueSeveral new VCO topologies are presented here, and it is shown that they can significantly enhance the power dissipation of the GHz CSVCOs.

Low Power Differential and Ring Voltage Controlled Oscillator Architectures for High Frequency (L-Band) Phase Lock Loop Applications in 0.35 Complementary Metal Oxide Semi Conductor Process

The design of a high frequency (L Band), low power (2.75mW) Phase Lock Loops with a 350nm Complementary Metal Oxide Semi Conductor (CMOS) technology has been represented. The comparison of Current Starved Voltage Controlled Oscillator (CSVCO) and Differential pair VCO is performed and analyzed for low power and high frequency analysis respectively. Each component of Phase Lock Loop (PLL) is designed with 350nm CMOS technology in Design Architect Integrated Circuit Station by Mentor Graphics (Eldo-Net) as simulator. In this paper both the standard configurations have been simulated under the same environment and results are analyzed for two most important Very Large Scale Integration (VLSI)constraints, Speed (High frequency range) and Power consumption. The high speed and locking performance of the Differential pair VCO has been evaluated against the lower power consumption benefit of CSVCO.

A highly linear current-starved VCO based on a linearized current control mechanism

A highly linear voltage controlled oscillator (VCO) suitable for emerging time-based and VCO-based applications is presented. By providing a very linear and high dynamic range biasing current for a current-starved ring-oscillator, improved linearity is achieved over rail-to-rail input control voltage. The input control voltage is first mapped by a resistive network and then is transformed to a biasing current by means of two linear voltage-to-current (V/I) converters with proportional and complementary behavior with respect to the control voltage. The difference between output currents of the V/I converters is utilized to enhance the linearity and frequency tuning range of the VCO. The proposed architecture is very compact and can be employed for most of current-starved ring oscillators regardless of delay element topology. Simulation results with a 1.8-V 0.18-μm standard CMOS technology show that for a rail-to-rail input voltage, the nonlinearity of frequency error using a simple single-ended delay element ranges from 0.02% to 0.9%. By using a differential delay element, the maximum frequency error reduces to 0.66%.

Ultra low power DG FinFET based voltage controlled oscillator circuits

ABSTRACTVoltage-controlled oscillator (VCO) significantly influences power and performance in many analog and digital applications. In this era of portable electronics, power consumption has emerged as an important design metric. Intended subthreshold circuits have proven their ability to satisfy this demand of ultra low-power consumption of a multitude of applications such as RFID, microsensors, etc. Double-gate Fin-FET technology is a promising alternative to the CMOS technology for the subthreshold circuits because of its enhanced gate control, improved performance, scalability, and robustness. Therefore, this paper investigates the viability of DG FinFET Current Starved Voltage Controlled Oscillator (CSVCO) in the subthreshold regime. The results indicate the superior performance of DG FinFET-based CSVCO in regard to speed, PDP, EDP, and variability as compared to CMOS-based CSVCO. Seven different CSVCO configurations, viz.. SG, IG, hybrid, hybrid reverse, pignsg, psgnig and MIGFET, designed using different configurations of DG FinFET, are simulated using 32 nm FinFET Predictive Technology Model (PTM) in HSPICE at 150 mv power supply. The proposed pignsg CSVCO shows better results in terms of frequency obtained versus power expended giving least PDP of 1.25E-16J and better immunity to supply voltage and process variations compared to all other CSVCO configurations.

Design of High frequency Voltage Controlled Oscillators for Phase Locked Loop

This paper presents the analysis of various oscillators that generate high frequency of oscillation for high speed communication, clock generation and clock recovery. The Ring oscillator and the Current Starved Voltage Controlled Oscillator(CSVCO) (for 5-stagewithout resistor and with resistor) have been implemented using the Cadence Virtuoso tool in 90 nm technology. The generated frequency of oscillation and the power consumption values of the voltage controlled oscillators have been calculated after inclusion in the PLL, and were also compared to identify the most suitable voltage controlled oscillator for a given application.

On-Chip Photovoltaic Power Harvesting System With Low-Overhead Adaptive MPPT for IoT Nodes

Extracting maximum power from a photovoltaic (PV) harvester with minimum power transfer loss is one of the primary design goals of an energy processing circuit. This paper presents a fully integrated PV power harvesting system with a low-overhead adaptive maximum power point tracking (MPPT) scheme for Internet-of-Things (IoT) nodes. The proposed scheme tracks the MPPs within 12 $\mu \text{s}$ by utilizing an inherent negative feedback loop, within a tracking error of 0.6%. The tracking range has been improved by ~57% using a current-starved voltage-controlled oscillator (CS-VCO) instead of a polynomial VCO. The overhead area and power consumed by this tracking scheme are approximately 0.013% and 0.1%, respectively. Using commercially available solar cell of area 11.3 cm2, the proposed system can provide 833 $\mu \text{W}$ of power with a light intensity of 600 lx. The proposed energy processing circuit has been designed using 0.18- $\mu \text{m}$ CMOS technology node and the circuit simulations demonstrate that the proposed scheme can track maximum power point (MPP) under rapidly changing atmospheric conditions with a peak tracking efficiency of 99%.

A Multiobjective Optimization Based Fast and Robust Design Methodology for Low Power and Low Phase Noise Current Starved VCO

This paper presents a novel design methodology for design of optimal and robust current starved voltage controlled oscillator (CSVCO) circuit. A recently developed multiobjective optimization technique infeasibility driven evolutionary algorithm is used to minimize the power and the phase noise of the circuit at its schematic and physical level. The multiobjective optimization is carried out by taking into account the extracted parasitics that would be present in the physical integrated circuit and the random variations of parameters during fabrication in foundry. This method helps the designer in semiconductor industry by effectively reducing several time consuming design iterations to a single iteration ensuring the near optimal performance of the CSVCO. The performance of the circuit is validated by carrying out simulations for transient and noise analysis in Cadence tools using 90 nm 1P9M CMOS process.

Effects of technology scaling on the SET sensitivity of RF CMOS Voltage-controlled oscillators

We analyze single-event transient (SET) effects in a high-speed voltage-controlled oscillator (VCO) design that is applicable to mixed-signal RF operations. Our study shows that the sensitivity of this type of circuit topologies exhibits a strong correlation to: the minimum feature size of the technology in use, the range of oscillating frequencies that the circuit is designed to achieve and the frequency at which the VCO is operating. We also determine that current-starved VCOs have an optimal functional range for improved radiation tolerance, located at the upper segment of their voltage-to-frequency transfer characteristic, where exposition to low LET ions become of no consequence on the operation of the circuit. More importantly, we show that derating the frequency of such VCO designed in a state-of-the-art technology does not compensate for the increased radiation vulnerability at that node. If not properly accounted for, the performance overhead that the newer technology provides is shown to severely penalize the radiation hardness of the circuit.