Current Squarer Circuit Research Articles

A linearly/electronically controllable high gain VDGA and its applications

Since the transconductance gains of an active building block namely voltage differencing gain amplifier (VDGA) is directly proportional to nonlinear (square root) function of external DC bias currents, affecting the narrow range tunability and low transconductance gains. This article aims to introduce a high gain VDGA by using CMOS current squaring circuits biasing in each transconductance cell. It offers high transconductance gains, wide range of tunability, linearity of controllability, larger input voltage range and nearly infinite input impedance. The proposed circuit was designed using a 0.18 µm CMOS transistors technology. The test was performed using PSpice program, it is consistent with the theoretical expectation. The total power consumption is 2.9 mW at ±1.5 V power supply. Even its power consumption is more than about 3 times of their previously proposed VDGAs, the figure of merit (FOM) of the proposed VDGA is much better than that of the previously proposed VDGAs (about 10 times). Additionally, the applications of the proposed VDGA as a capacitance multiplier, current multiplier/divider, summing amplifier, independently/electronically tunable multifunction filter, precision half-wave and full-wave rectifiers are included to insist the workability of the proposed VDGA.

0.8‐V 1.4‐nW multi‐decade frequency range true RMS to DC converter based on two‐quadrant current squarer circuit

A low-voltage ultra-low-power two-quadrant current squarer based-true RMS to DC converter circuit is presented in this study. The proposed current squarer is based on two translinear loops with matched NMOS transistors operating in the weak inversion region. Ultra-low-power dissipation of 1.4 nW, multi-decade frequency range of 0.5 Hz–55 kHz and large input dynamic range of 72 pA–1 nA (with error <3%) are the main achievements of the proposed design while constructed of only ten transistors. Post-layout simulations with 0.8-V supply voltage using HSPICE software in 0.18 μm TSMC CMOS process (level-49 parameters) verified the good functionality of the proposed circuit. Moreover, Monte Carlo analysis is performed to validate the satisfactory PVT robustness and reliability of the design's performance.

Compact Design of High-Speed Low-Error Four-Quadrant Current Multiplier with Reduced Power Dissipation

In this paper, a compact low-power, high-speed, low-error four-quadrant analog multiplier is proposed using a new simple current squarer circuit. The new squarer circuit consists of an NMOS transistor, which operates in saturation region, plus a resistor. The proposed multiplier has a balanced structure composed of four squarer cells and a simple current mirror. This multiplier also has the important property of not using bias currents which results in greatly reduced power. The performance of the proposed design (for passive and active realization of the resistors) has been simulated using HSPICE software in 0.18[Formula: see text][Formula: see text]m TSMC (level-49) CMOS technology. Simulation results with [Formula: see text]-V DC supply voltages show (for passive realization) that the maximum linearity error is 0.35%, the [Formula: see text][Formula: see text]dB bandwidth (BW) is 903[Formula: see text]MHz, the total harmonic distortion (THD) is 0.3% (at 1[Formula: see text]MHz), and the maximum and static power consumption are [Formula: see text]W and [Formula: see text]W, respectively. Also, post-layout simulation results are extracted, which give the maximum linearity error as 0.4%, the [Formula: see text][Formula: see text]dB BW as 657[Formula: see text]MHz and the THD as 0.35%, as well. Moreover, Monte Carlo analysis are performed to verify the satisfactory robustness and reliability of the proposed work’s performance.

Low-Power High-Speed Analog Multiplier/Divider Based on a New Current Squarer Circuit

In this paper, a CMOS ultra-low-power, high-speed four-quadrant current multiplier/divider circuit is presented. Based on square-difference approach, the proposed circuit is using a new current squarer with MOS transistors operating in weak inversion region. The translinear loops are the basic building blocks in realization of the current-mode two-quadrant squarer and four-quadrant multiplier/divider circuits. The proposed designs have been simulated using HSPICE in 0.18 $$\upmu \hbox {m}$$ TSMC CMOS (level-49 parameter) process. Post-layout simulation results with 0.8 V power supply show the total power dissipation of 770 nW, the total harmonic distortion of 0.67% (at 100 kHz), the maximum linearity error of 2%, and the − 3 dB bandwidth of 34.1 MHz. Monte Carlo analysis is also performed to ensure the stability and robustness of the circuit’s performance in the presence of the PVT (process, voltage, and temperature) variations.

Comments on "Improved Accuracy Pseudo-Exponential Function Generator With Applications in Analog Signal Processing

Recently a new CMOS current-mode pseudo-exponential function generator circuit was reported by Popa. The entire analysis and exponential function generator circuit, given in Popa's paper, is based on a current-squaring circuit module. In this comment paper we show that the current-squarer circuit, presented in Popa's paper, does not work as a current squarer. Consequently the pseudo-exponential generator also does not work as described in Popa's paper. We present a detailed mathematical analysis in this paper to derive its actual operation. Simulation results of the circuit module using Mentor Graphics custom IC design tool set, in a TSMC 0.18-μm CMOS process, are also shown in this paper. Simulation results match the behavior predicted by mathematical analysis.

A Low-Power K-Band CMOS Current-Mode Up-Conversion Mixer Integrated with VCO

SUMMARY A low-power K-band CMOS current-mode up-conversion mixer is proposed. The proposed mixer is realized using four analog current-squaring circuits. This current-mode up-conversion mixer is fabricated in 0.13-μm 1P8M triple-well CMOS process, and has the measured power conversion gain of −5 dB. The fabricated CMOS up-conversion mixer dissipates only 3.1 mW from a 1-V supply voltage. The VCO can be tuned from 20.8 GHz to 22.7 GHz. Its phase noise is −108 dBc/Hz at 10-MHz offset frequency. It is shown that the proposed mixer has great potential for low-voltage and low-power CMOS transmitter front-ends in

A differential active load and its applications in CMOS analog circuit designs

In this paper we describe a CMOS differential active load and show how it can be used to create various useful structures. Tunable current gain stages and current squaring circuits are discussed. Their connection to a differential pair-based transconductor results in broad-range tunable transconductor structures suitable for adaptive continuous-time filtering applications and a four-quadrant voltage multiplier.

A class AB CMOS tunable voltage-to-current converter

In this paper, a CMOS-based electronically tunable voltage-to-current (V/I) converter, which is realized using class AB amplifiers and current-squaring circuits, is proposed. The circuit provides an ability to vary its transconductance gain by electronic means with low input impedance, wide dynamic range and wide bandwidth. SPICE simulation results, which show the linearity and accuracy of the converter and the application examples of the V/I are given.

Novel analogue CMOS defuzzification circuit

An analogue CMOS circuit technique for the implementation of defuzzification is proposed. The defuzzification method is based upon the normalisation locked loop (NLL) method, but with two key improvements: the compact representation of triangular membership functions, and a mechanism to ensure that the relative rule weight proportions are preserved during normalisation. Circuit complexity is considerably reduced by combining these two operations in a single circuit stage. The proposed weight circuit, which evaluates normalised rule weights, has been realised using current squaring circuits proposed by Bult and Wallinga (1987). The weight circuit has been fabricated in a 2.0 µm CMOS process. Results obtained from the fabricated circuit operating as part of a NLL are presented.

Cmos-based electronically tunable current conveyor

A CMOS-based small signal current amplifier, which is constructed from two current-squaring circuits with improved dynamic range is introduced. A circuit technique for realising an integrable electronically tunable current conveyor that is designed around the current amplifier is proposed. >

A class of analog CMOS circuits based on the square-law characteristic of an MOS transistor in saturation

The examined class of circuits includes voltage multipliers, current multipliers, linear V-I convertors, linear I-V convertors, current squaring circuits, and current divider circuits. Typical for these circuits is an independent control of the sum as well as the difference between two gate-source voltages. As direct use is made of the basic device characteristics, only a small number of transistors is required in the presented circuits.