Current Reuse Circuit Research Articles

A Low Impedance Current-Reuse Path for UWB-PA to Improve Efficiency and Gain

Current-reuse circuit with a low impedance current-reuse path has been proposed to enrich high flat gain, high efficiency, and high output power across the operating band. While an inductor-capacitor (LC) interstage is employed to improve the linearity of the proposed PA. In the second stage, the shunt peaking design in a common-source circuit is employed to improve the power gain, while a network of reactance compensation is adopted at the output of the second stage to overcome the parasitic capacitance's impact on the active device. The post-layout simulation using the TSMC 65 nm CMOS process is carried out on the entire frequency range from 3.1 GHz to 10.6 GHz. The post-layout simulation achieved ±42 ps group delay variation, 32% power-added efficiency (PAE), and 32-dB power gain. Matching input and output of less than −10 dB has been achieved over the operating band, and it achieved an output power of 18.3 dBm.

Highly efficient W‐band 2.5 GHz bandwidth pulse generator with −1 dBm output power in 65 nm CMOS

A W-band 2.5 GHz bandwidth pulse generator comprising a voltage-controlled oscillator (VCO) and a novel pulse former in a 65 nm CMOS technology is presented. The proposed sub-harmonic pumped pulse former, which plays roles as both a frequency doubler and a pulse former, is designed to obtain high efficiency using a transformer-based current reuse circuit. The VCO is implemented with a parallel combining transformer, which makes it insensitive to load variations due to pulse formation. Measurements show that the pulse generator achieves −1 dBm peak output power at 79 GHz. It can generate 800 ps pulse signals with an RF carrier of 76.1–79.6 GHz, achieving the energy cost rate of 50 pJ/pulse with a 1.25 GHz pulse repetition period.

A W-Band High-Efficiency CMOS Differential Current-Reused Frequency Doubler

A W-band differential frequency doubler using a current-reuse configuration in a 65 nm CMOS process is presented in this letter. The differential current-reuse circuit with a second harmonic coupling transformer is introduced to improve conversion gain at small input powers minimizing the effect of the RF bypass capacitor. The proposed circuit achieves a conversion gain of $0.8\sim -4.2~{\rm dB}$ and a fundamental rejection above 19 dB in the input frequency range of 36.5~44 GHz with $-4 ~{\rm dBm}$ input power. It has conversion gain variation below 1 dB when the input power varies from $-7.4$ to 0.1 dBm at 77 GHz. The dc power consumption is 14 mW. It has the highest conversion gain with the smallest chip size of 0.22 ${\rm mm}^{2}$ among all V-/W-band CMOS frequency doublers.

A 5.25-GHz CMOS folded-cascode even-harmonic mixer for low-voltage applications

This paper presents a 5.25-GHz folded-cascode even-harmonic mixer (FEHM) for low-voltage applications. This FEHM employs the folded technique to reduce the headroom voltage, a current reuse circuit in the RF stage to improve its linearity, and the frequency-doubling technique in the local oscillator (LO) stage to produce an LO double-frequency signal. In addition, the proposed technique exhibits the advantage of high conversion gain. In order to demonstrate the benefits and optimize the circuit design, the theoretical studies of conversion gain, linearity, and noise performance are described. For measurement, the proposed FEHM possesses conversion gain of 8.3 dB, third-order input intercept point (IIP/sub 3/) of 0.03 dBm, and second-order input intercept point (IIP/sub 2/) of 31.2 dBm under the supply voltage of 0.9 V and LO power of 5.5 dBm. The power consumption of the proposed mixer is about 4.95 mW at an IF frequency of 500 kHz.

Analysis and implementation of a CMOS even harmonic mixer with current reuse for heterodyne/direct conversion receivers

This paper presents a novel topology for the even harmonic mixer (EHM). The proposed mixer employs a current reuse circuit in the RF input stage to improve its linearity, and uses the double frequency technique in the LO input stage to overcome the leakage and dc offset problems for heterodyne and direct conversion receivers, respectively. In addition, the proposed topology also has the advantages of low power consumption and high conversion gain. In order to demonstrate the benefits of the proposed mixer, theoretical analyses of linearity, conversion gain, and noise performance have been described in detail. The measured results reveal that the proposed mixer has a single-end conversion gain of 9.17 dB, third-order input intercept point (IIP/sub 3/) of -5.01 dBm, and IIP/sub 3//dc of -6.31 dB, under the supply voltage of 1.8 V, power consumption of 1.35 mW, and LO power of 5 dBm at 900 MHz.

A 1.8-V operation 5-GHz-band CMOS frequency doubler using current-reuse circuit design technique

This paper describes the circuit design and measurement results of a new CMOS frequency doubler proposed for 5-GHz-band wireless applications. The doubler, which can operate at 1.8 V, was fabricated in a standard 0.18-/spl mu/m bulk CMOS technology which has no extra processing steps to enhance RF performance. A current-reuse circuit-design technique is successfully incorporated into the doubler so as to realize both on-chip input/output matching and adequate conversion gain with low input power drive despite the utilization of the standard bulk CMOS technology. The doubler with a single input/output interface features a bypass resistor placed between common ground and a source node of the second stage FET in the current-reuse topology, thereby improving both input power level and conversion gain while saving waste current. Measurement results under the condition of 5.2 GHz and 1.8 V reveal the following good performance: a 2.7-dB maximum conversion gain, a 0.3-dBm high output power, and a 9-mA low current dissipation are achieved with a 2.6-GHz, -3-dBm input power. With a 7-mA low current dissipation and a -7-dBm low input power, the doubler can deliver conversion gain as high as 0 dB. These measurement results are good agreement with the simulated ones.