Current Mode Successive Approximation Research Articles

A 5G FR2 Power-Amplifier With an Integrated Power-Detector for Closed-Loop EIRP Control

A fifth-generation (5G) frequency range 2 (FR2) transmitter front end with a fully integrated power detector for enabling closed-loop power control is presented. The power detection path includes a miniature broad-side directional coupler, a sense pair, and a current-mode successive approximation analog-to-digital converter. The stacked power amplifier (PA) implemented in a 28-nm CMOS silicon on insulator (SOI) process delivers 12.5-dBm output power with a power-added efficiency of 10% and an error vector magnitude (EVM) lower than −25 dB with a CP-OFDM/64-QAM/400-MHz bandwidth signal. The PA supports 5G frequency bands n257/n258/n261 covering a frequency range from 24.25 to 29.5 GHz. With a matched output load, the power detector has less than ±0.15-dB error over a 15-dB power dynamic range and 85° temperature range.

Low power and adjustable biomedical sensor interface system

In this paper a new sensor interface using current mode approach is presented for biomedical applications. The proposed sensor interface utilises a low-power current-mode comparator, an 8 bit current mode successive approximation analogue to digital converter (SA-ADC), an adaptable band-pass filter as well as a highly linear transconductance amplifier (Gm). The Gm and current mode SAR ADC are designed in a way to achieve minimum power consumption. The circuit is simulated in 0.18 μm CMOS technology with supply voltage of 1.8 V. At 400 KS/s sampling frequency, the total power consumption and total harmonic distortion of the system are obtained equal to 2.2 μW and 45.2 dB respectively. The simulation results demonstrate the effectiveness and superiority of the proposed circuit in comparison with the conventional circuits.

Behavioral non-ideal Model of 8-bit Current-Mode Successive Approximation Registers ADC by using Simulink

In this paper a new non-ideal model of 8-bit Current Mode Successive Approximation Analog-Digital Converter (CM-SAR-ADC) has been proposed, the main blocks of CM SAR ADC are a current sample and hold, a current comparator, SAR logic register and current steering digital to analogue converter (DAC). The model is implemented in Matlab Simulink environment with non ideals factors such as switching noise, clock feed through, charge injection, flicker noise, clock jitter, settling error, and the effect of MOS transistor mismatch in the current sample and hold(S/H) and in the current steering DAC models, the delay time and the current offset are introduced as non-ideal sources to the current comparator model. The comparisons of the simulation results using 8-bits CM SAR ADC with ideal and non-ideal models confirmed the effects of the non ideality sources on the parameters of the ADC.

A Current Mode Successive Approximation ADC for Focal Plane Integration

A Current Mode Successive Approximation ADC for Focal Plane Integration