Current-mode Passive Mixer Research Articles

2.4-GHz Low-Power Low-IF Receiver With a Quadrature Local Oscillator Buffer for Bluetooth Low Energy Applications

In this brief, a 2.4-GHz low-power single-quadrature low-IF Bluetooth low energy receiver employing a quadrature local oscillator (LO) buffer is presented for Internet of Things applications. The quadrature LO buffer, which consists of common-source amplifiers with capacitive degeneration, compensating resistors, compensating PMOS transistors and LC tanks, performs quadrature generation and supplies quadrature signals to a single-quadrature mixer, thus eliminating an additional circuitry for quadrature generation in the LO path and saving dc current consumption. The implemented receiver consists of a low-noise amplifier, a G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -stage, double-balanced current-mode passive mixers, transimpedance amplifiers, an active- RC complex bandpass filter, and the quadrature LO buffer. Fabricated in a 65-nm CMOS process, the implemented receiver achieves a noise figure of 8.16 dB, a conversion gain of 54.5 dB, an image rejection ratio of 32.1 dB, and an input-referred third-order intercept point of -27.5 dBm. It draws a bias current of 2.5 mA from a nominal supply voltage of 0.8 V, and the active die area is 1.65 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

2.4 GHz BLE Receiver With Power-Efficient Quadrature RF-to-Baseband-Current-Reuse Architecture for Low-Power IoT Applications

In this paper, a 2.4 GHz Bluetooth low energy receiver employing a power-efficient quadrature RF-to-baseband-current-reuse architecture is presented for low-power low-voltage internet of things applications. The proposed quadrature RF-to-baseband-current-reuse RF front-end consists of a low-noise transconductance amplifier, an active-type polyphase filter-based quadrature generator, transimpedance amplifiers, and double-balanced current-mode passive mixers on a single dc current path. An input matching network is used to perform power-constrained simultaneous noise and input power matching and 1/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f$ </tex-math></inline-formula> noise reduction in the RF and baseband domains, respectively. The quadrature RF signals are provided to the single-quadrature mixers through an embedded active-type polyphase filter-based quadrature generator. The implemented Bluetooth low energy receiver is composed of the RF-to-baseband-current-reuse RF front-end, IF amplifiers, two-stage passive- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> polyphase filter, and fifth-order Chebyshev-II <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m}$ </tex-math></inline-formula> <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-C</i> filters. The proposed design was fabricated using a 65-nm CMOS process and characterized primarily in the Bluetooth low energy operating frequency bands. The active die area of the implemented receiver was 0.85 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the receiver drew a bias current of 1.41 mA from a nominal supply voltage of 0.8 V. The Bluetooth low energy receiver achieved a noise figure of 13.2 dB, conversion gain of 42 dB, image rejection ratio of more than 30 dB, and input-referred third-order intercept point of −25 dBm.

2.4-GHz Bluetooth Low Energy Receiver Employing New Quadrature Low-Noise Amplifier for Low-Power Low-Voltage IoT Applications

In this article, a 2.4-GHz Bluetooth low-energy (BLE) receiver employing a new quadrature low-noise amplifier (LNA) is presented for low-power low-voltage Internet of Things (IoT) applications. The proposed quadrature LNA consists of a common-source (CS) amplifier with inductive degeneration, an active-type poly-phase filter (PPF), and an LC tank. The proposed active-type PPF between the CS amplifier and the LC tank provides quadrature generation, and the CS amplifier determines and optimizes the overall LNA performance parameters. Moreover, the proposed active-type PPF shares the dc bias current with the CS amplifier, thereby eliminating the necessity for additional current consumption. The implemented BLE receiver is composed of the quadrature LNA, a $G_{m}$ -stage, a double-balanced current-mode passive mixer, a transimpedance amplifier, and an active- RC complex bandpass filter. The proposed design was fabricated in a 65-nm CMOS process and mainly characterized in the BLE operating frequency bands. The receiver achieves a noise figure of 8.2 dB, a conversion gain of 49.5 dB, an image rejection ratio of more than 33 dB, and an IIP3 of −25.75 dBm. The active die area of the implemented receiver is 1.16 mm2, and it draws a bias current of 2.7 mA from a nominal supply voltage of 0.8 V.

A Low-Power RF-to-BB-Current-Reuse Receiver Employing Simultaneous Noise and Input Matching and 1/$f$ Noise Reduction for IoT Applications

A low-power low-noise RF-to-baseband (BB)-current-reuse quadrature receiver employing simultaneous noise and input power matching and 1/ $f$ noise reduction technique is proposed for the Internet of Things applications. The receiver shares bias current between a low-noise transconductor and a transimpedance amplifier with single supply voltage and employs a double-balanced current-mode passive mixer with 25% duty-cycle local oscillator (LO), thereby reducing power consumption. To improve noise performance in the direct-conversion or low-IF receiver, the proposed receiver architecture performs simultaneous noise and input power matching at the RF domain and 1/ $f$ noise reduction at the BB domain. The presented prototype, implemented in the 65-nm CMOS process, occupies an active die area of 0.559 mm2 while consuming 3.6 mW at a supply voltage of 1.8 V. It achieves a voltage gain of 40.7 dB, an noise figure (NF) of 1.94 dB, $S_{11}$ of less than −10 dB, and an IIP3 of −25.6 dBm.

Design and Analysis of a Broadband Current-Mode CMOS Direct-Conversion Receiver Frond-End Circuit

A broadband (0.8–5[Formula: see text]GHz) CMOS current-mode direct-conversion receiver has been integrated in a 0.18-[Formula: see text]m CMOS process. The proposed receiver front-end features a broadband active-balun low-noise transconductance amplifier (LNTA) driving a current-mode passive mixer terminated by a low-input-impedance transimpedance amplifier (TIA). The receiver chain has improved robustness to out-of-band interference, conversion gain and outstanding linearity. With the technique of noise and distortion cancellation which performs a better input impedance matching, we employ a broadband common-gate–common-source (CG–CS) LNTA and a current mirror to improve both gain and noise figure (NF) performance. Compared to the 50% duty-cycle switching stage, the 25% duty-cycle I–Q switching stage is implemented by using serial switches driven by 50% quadrature local oscillator (LO) signals separately, which improves the down-conversion gain by 3[Formula: see text]dB and lowers the noise figure. The transimpedance amplifier employs the [Formula: see text]-boosting technique to realize low input impedance and high transimpedance gain. The core circuit (RF and baseband signal path) consumes 26[Formula: see text]mW, and the prototype receiver achieves approximately 33–34.5-dB conversion gain, 8.1–9.35-dB NF and 7.5–9.8-dBm IIP3 from 0.8[Formula: see text]GHz to 5[Formula: see text]GHz.

A Coupled-RTWO-Based Subharmonic Receiver Front End for 5G &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$E$ &lt;/tex-math&gt; &lt;/inline-formula&gt;-Band Backhaul Links in 28-nm Bulk CMOS

An $E$ -band direct-conversion subharmonic receiver (SHRX) is designed exploring a coupled-rotary-traveling-wave-oscillator-based (coupled-RTWO-based) architecture. Distributed oscillators are leveraged to generate $N=8$ differential phases at $f_{\mathrm{ LO}}=f_{\mathrm{ RF}}/4$ . Current-mode passive mixers (MXs) are adopted to enable <1-V supply operation and greatly simplify the layout. An inductively degenerated neutralized common source (DCS) low-noise amplifier (LNA) is embedded in a fourth-order transformer-based matching network to allow broadband impedance scaling and high reverse isolation. Implemented in a 28-nm bulk CMOS technology without ultra-thick top metal option, the realized prototype outperforms prior reported CMOS designs in terms of phase noise, figure of merit (FOM), and tuning range. The SHRX front end achieves 8.3-dB noise figure (NF), 12.5 GHz −3-dB RF bandwidth (BW), and −25-dBm ICP1 dB, while consuming <100 mW.

40-nm CMOS Wideband High-IF Receiver Using a Modified Charge-Sharing Bandpass Filter to Boost Q-Factor

A 40-nm CMOS wideband high-IF receiver is presented in this paper. The low-noise transconductance amplifier (LNTA) uses dual noise cancellation in order to improve its noise figure. The LNTA has also a folded-cascode structure to increase its output impedance and prepare for a current-mode passive mixer. This structure is merged into the output stage of the LNTA, so there is no need for extra transistors. Additionally, a modified charge-sharing bandpass filter with cross-connected transconductors to boost Q-factor is proposed and discussed. The highest voltage gain achieved by the receiver (RX) is 30 dB. The RX noise figure is 3.3 dB at the maximum gain, while the IIP3 is −2.5 dBm at 1 GHz. The area of the receiver is very competitive for the wide band considered, merely 0.137 mm2. The RX and clock generation circuitry drain 25 mA from a 0.9-V supply.

A SAW-Less 2.4-GHz Receiver Front-End With 2.4-mA Battery Current for SoC Coexistence

A 2.4-GHz receiver for short-range communications with +6 dBm out-of-band IIP3 and only 2.4-mA battery current is presented. The single-ended input is coupled through an integrated transformer to a push–pull differential low-noise transconductance amplifier (LNTA) followed by a current mode passive mixer that drives a single-opamp biquad trans-impedance amplifier. This approach ensures sufficient linearity to enable coexistence with large out-of-band interference arising from other on-chip/on-board transceivers. An efficient block stacking technique is proposed to minimize the current drawn from a standard 1.8-V supply. The first stages of the two opamps used in the I and Q baseband Rauch filters are placed above and below the LNTA core, thereby sharing its dc current. Two active inductors isolate the RF and baseband signal paths. Several techniques are used to limit the impact of the 1/f noise of the RF blocks on the receiver and to minimize nonlinearities due to interactions between blocks sharing the same current. The entire receive signal path draws 2.4 mA from a 1.8-V supply and has a noise figure of 7.8 dB at 2.4 GHz and an out-of-band 1-dB compression point of −5 dBm. The chip, implemented in 28-nm LP CMOS, occupies an active area of 0.4 mm2.

A 77 GHz Frequency Doubling Two-Path Phased-Array FMCW Transceiver for Automotive Radar

A fully-integrated 77 GHz frequency doubling two-path phased-array frequency-modulated continuous-wave (FMCW) transceiver for automotive radar applications is proposed. By utilizing the frequency doubling scheme, the chirp bandwidth is improved, and the complexity of the frequency synthesizer and the insertion loss of the local-oscillating (LO) distribution network are both reduced. Top-injected coupled resonator based wide locking range technique is proposed in the frequency doublers to minimize the required injection power to cover the chirp bandwidth plus enough PVT variation margin, and therefore reduce the power consumption of the LO distribution network. Current-reused coupled resonator technique is utilized to implement the LO phase shifting in each receiving path. The digitally controlled artificial dielectric-based transmission lines are inserted in the low noise amplifiers to provide the operation frequency calibration capability. The receiving two-path signals are converted into intermediate frequency by low flicker noise current-mode passive mixers and then combined in the trans-impedance amplifier, followed by the reconfigurable analog baseband processing. Fabricated in 65 nm CMOS, the FMCW transceiver has achieved 1.93 GHz maximum chirp bandwidth, 12.9 ~ 13.2 dBm maximum transmitting power, and 47.8 ~ 100.7 dB programmable receiving conversion gain. The transceiver consumes 343 mW power and 4.64 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip area including all of the pads.

A Noise-Cancelling Receiver Front-End With Frequency Selective Input Matching

This paper presents an inductor-less frequency selective input match wireless receiver front-end utilizing noise cancellation, operational from 0.7 to 3.8 GHz. The main path of the receiver consists of a high input impedance transconductance stage where the output is down-converted to baseband by current mode passive mixers, and then amplified to voltage by a transimpedance amplifier. The output voltage is converted into a current and frequency up-converted by a second set of transconductance stage and mixer. This current is then fed back to the input of the main path, reducing the input impedance, providing input match by means of negative feedback. An auxiliary path with digitally controllable gain is also introduced to cancel the noise of the main path while maintaining high linearity. The chip prototype is fabricated in a 65 nm CMOS process and occupies an active area of 0.15 mm $^2$ . It achieves a noise figure between 1.6 dB and 3.2 dB depending on the frequency of operation, and an out-of-band IIP2 and IIP3 better than +75 dBm and +1 dBm, respectively. The chip is supplied by 1.2 V and consumes 22.8–34.9 mA.

Low-Power, Low-Cost CMOS Direct-Conversion Receiver Front-End for Multistandard Applications

A broadband CMOS direct-conversion receiver with on-chip frequency divider has been integrated in a 0.13- μm CMOS process. The key feature of the proposed receiver front-end is a single low-noise transconductance amplifier (LNTA) driving a current-mode passive mixer terminated by a low-input-impedance transimpedance amplifier (TIA). The receiver chain has improved robustness to out-of-band interference and outstanding linearity. We employ a broadband common-gate (CG) LNTA with dual feedback to improve both gain and noise figure (NF) without breaking the fixed relationship between input impedance, transconductance gain, and load impedance. A LNTA load impedance boosting technique suppresses noise-amplification due to TIA, commonly found in passive mixers. The core circuit (RF and baseband signal path) consumes only 13 mW, and the prototype receiver achieves >22.4-dB conversion gain, dB NF, and ≥ -1.5 dBm IIP3 from 1.4 to 5.2 GHz. Maximum conversion gain of 24.3 dB and minimum NF of 6.5 dB are achieved at 1.4 and 2 GHz, respectively. The chip active area is 1.1 mm 2 with the entire RF signal path operated from a 1.2-V supply. The LO portion is biased from a 1.5-V supply.

A High-Linearity WCDMA/GSM Reconfigurable Transceiver in 0.13-$\mu\hbox{m}$ CMOS

This paper presents a dual-mode multiband transceiver with DigRF interface implemented in a 0.13-μm CMOS technology. Based on direct conversion architecture, blocks in the transceiver can be configured to simultaneously support wavelength code-division multiple access (WCDMA) band I and four Global System for Mobile Communications (GSM) bands (PCS/DCS/GSM900/GSM850). In the receiver path, the narrowband radio-frequency front-end is comprised of multiple-gated low-noise amplifiers with capacitive desensitization and current-mode passive mixers with the proposed second-order input intercept point (IIP2) calibration to comply for surface-acoustic-wave-less application. In the transmitter path, a high-linearity mixer and parallel Class-AB PA driver are adopted. Low-noise wideband frequency synthesizers with adaptive frequency calibration are proposed to cover all modes and bands. This reconfigurable transceiver achieves -5.6/-2/-6 dBm in-band third-order intercept point for WCDMA/GSM HB/GSM LB respectively, and >;65 dBm IIP2. At the maximum output power, the transmitter achieves 2.3% rms error vector magnitude for WCDMA I and 1.67° phase error for a GSM system.

Analysis and design of a high-linearity receiver RF front-end with an improved 25%-duty-cycle LO generator for WCDMA/GSM applications

A fully integrated receiver RF front-end that meets WCDMA/GSM system requirements is presented. It supports SAW-less operation for WCDMA. To improve the linearity in terms of both IP3 and IP2, the RF front-end is comprised of multiple-gated LNAs with capacitive desensitization, current-mode passive mixers with the proposed IP2 calibration circuit and reconfigurable Tow-Thomas-like biquad TIAs. A new power-saving multi-mode divider with low phase noise is proposed to provide the 4-phase 25%-duty-cycle LO. In addition, a constant-gm biasing with a non-chip resistor is adopted to make the conversion gain invulnerable to the process and temperature variations of the transimpedance. This RF front-end is integrated in a receiver with an on-chip frequency synthesizer in 0.13 μm CMOS. The measurement results show that owing to this high-linearity RF front-end, the receiver achieves −6 dBm IIP3 and better than +60 dBm IIP2 for all modes and bands.

A 5 GHz 7.2 dB NF low power direct conversion receiver front-end with balun LNA

A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted, and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor. To obtain low 1/f noise and high linearity, a current mode passive mixer is preferred and realized. A current mode switching scheme can switch between high and low gain modes, and meanwhile it can not only perform good linearity but save power consumption at low gain mode. The front-end chip is manufactured on a 0.13-μm CMOS process and occupies an active chip area of 1.2 mm2. It achieves 35 dB conversion gain across 4.9–5.1 GHz, a noise figure of 7.2 dB and an IIP3 of −16.8 dBm, while consuming 28.4 mA from a 1.2 V power supply at high gain mode. Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode.

A Low-Power RF Direct-Conversion Receiver/Transmitter for 2.4-GHz-Band IEEE 802.15.4 Standard in 0.18-$\mu{\hbox {m}}$ CMOS Technology

This paper presents a low-power RF receiver/transmitter front-end for 2.4-GHz-band IEEE 802.15.4 standard in 0.18-mum CMOS technology. An RF receiver comprises a single-ended low-noise amplifier, a quadrature passive mixer, and a transimpedance amplifier. A current-mode passive mixer showing a very good 1/f noise performance is adopted to convert an RF signal directly to a baseband signal. Moreover, this type of passive mixer shows high-linearity performance, leading to overall RF receiver linearity improvement. A low-power, high-linearity transmitter front-end is implemented by using a passive mixer and two-stage driver amplifier in which the first stage is a conventional cascode amplifier and the second stage uses a folded cascode one. The receiver front-end achieves 30-dB voltage conversion gain, 7.3-dB noise figure with 1/f noise corner frequency of 70 kHz, -8-dBm input third-order intercept point, and +40-dBm input second-order intercept point. The transmitter front-end shows 12-dB power conversion gain, 0-dBm output power with 10-dBm output third-order intercept point, and -30-dB local-oscillator suppression. The receiver and transmitter front-end dissipate 3.5 and 3 mA from a 1.8-V supply, respectively