Current-mode DC Research Articles

A Current-Mode DC–DC Buck Converter With Accurate Current Limit Using Multiplex PWM Comparator

In a conventional current-mode dc–dc buck converter, two sensed inductor current signals are processed in three separate comparators to regulate the converter under various load conditions. These independent sensing currents and comparators not only consume large quiescent current and silicon areas but also cannot guarantee the accuracy of the current limit threshold. This article proposes a current-mode dc–dc buck converter with an accurate current limit using a multiplex pulsewidth modulation (PWM) comparator. Through a multiplex PWM comparator, only one sensing current and one comparator are required to process the inductor current information and complete the regulation of the converter under various load conditions. The response speed of overcurrent protection is also increased without consuming more power and silicon area. Moreover, by generating the zero temperature coefficient (ZTC) sensing current and adding ZTC reference current with slope compensation information, the accuracy of the current limit threshold is greatly improved under various temperatures in a wide input voltage range. The proposed buck converter with a multiplex PWM comparator was fabricated using a standard 1P3M 0.18 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m BCD (BiCMOS/DMOS) process and the experimental results show that the proposed scheme functions properly in the 5-A load range, and the current limit threshold also varies only 8.1% in the temperature range from −40 to 125 °C with the input voltage up to 60 V.

Static Analysis of a Digital Peak Current Mode Control DC–DC Converter Using Current–Frequency Conversion

The purpose of this article is to discuss the design guideline and design chart of the digital peak current mode dc–dc converter using a current–frequency conversion by analyzing its static characteristics. The operation of the proposed method is expressed by equations, and the relationships between controller parameters are derived. This discussion reveals the relationships between the peak current instruction value and the output voltage or peak current, which are necessary for designing the proposed method. Then, the design guideline and design chart are given. The validity of the static characteristic analysis is demonstrated by a prototype, whose design follows the design guideline. An appropriate operation in the steady and static state is also indicated by the experiment. As a result, the validity of the static characteristics and the design guideline of the proposed method can be verified.

Adaptive frequency adjustment technique in current mode DC–DC converters for input voltage range extension

This study presents a switching frequency adjustment technique that helps widen the input voltage range of a current mode DC-DC converter. Conventional current-mode switching converters suffer the minimum on/off time restrictions that limit the input-to-output conversion ratio. This work introduces an additional regulation loop on top of an existing converter that regulates the switching period when the minimum on/off time limit is approached. Compared with a converter with fixed switching frequency, the proposed approach allows the free-running switching to be set without being limited by the minimum on/off time. A boost topology with output voltage of 24 V was built based on the proposed approach, and the measured valid input voltage range was extended from 8-16 to 3-21 V by the proposed scheme under 1 MHz preset frequency. Since the slope-compensation current, the inductor size, and the output capacitor are all optimised at 1 MHz and is not limited by the minimum on/off time which may lower the switching frequency of a conventional converter down to 450 kHz, the measured maximum available output current and the typical output voltage ripple under 12 V input achieved 1.57 A and 57 mV, respectively.

Frequency-Domain Power Delivery Network Self-Characterization in FPGAs for Improved System Reliability

Modern field-programmable gate arrays (FPGAs) operate at a core voltage around 1 V and therefore even small voltage fluctuations lead to timing violations and logic errors. The power delivery network (PDN) between the voltage regulator and the FPGA core must be carefully designed to achieve a low output impedance over a broad range of frequencies. Simulation tools are commonly used to estimate the impedance, however, they do not account for aging, component variations, and inaccurate modeling of parasitic elements, all of which lead to PDN design deviation. In this paper, two schemes are presented: first, to extract the dc resistance in the power delivery path, and second, to identify the high impedance frequency band(s) in the PDN. The embedded impedance extraction tool is synthesized within the FPGA load, in coordination with a mixed-signal current-mode dc–dc converter. A new self-calibrated carry-chain-based analog-to-digital converter (CC-ADC) is used for high-speed sampling of the core voltage. The proposed schemes are demonstrated on an Intel Cyclone IV FPGA board. Real-time IR -drop compensation is shown to eliminate logic errors in an finite impulse response filter application. It is also shown that the fail/pass map of a crossbar application matches well with the extracted impedance profile versus voltage and frequency. By modifying the PDN based on the extracted results, the voltage operating range and reliability of the crossbar application are greatly extended.

Analysis and control of chaotic behavior in boost converter by ramp compensation based on Lyapunov exponents assignment: theoretical and experimental investigation

Nonlinear analysis of complex dynamics displayed by current mode dc–dc converter and idea of Lyapunov exponents assignment by ramp compensator in order to control chaotic behavior is proposed in this article. A discrete-time iterative nonlinear mapping model is derived. The occurrence of the complex behaviors of bifurcation and chaos generated by varying the circuit parameters are investigated through numerical analysis and software implementation of the circuit. Next, in order to control bifurcation and chaos in these converters, the ramp compensation method is used. By inserting the ramp compensation parameter in the dynamical equations of the system, these complex behaviors are examined theoretically and numerically as well. It is proved that through this method, the stable period-one operation of the converter can be extended. By evaluating the Lyapunov exponents (LEs) of the system, the impact of the slope on the location of LEs are determined analytically. This leads to a design methodology for control of chaos in this converter based on LEs assignment in desired values by proper selection of compensator slope. By developing an experimental set up, practical results are obtained to confirm the theoretical analysis and simulations.

Pseudo-V2 control with adaptive compensation for fast-transient current-mode buck converter

A type of pseudo-V2 control, with on-chip adaptive compensation to achieve fast transient (FT) response for current mode DC–DC buck converter, has been proposed and simulated using 0.18μm CMOS technology in this paper. Based on a new on-chip capacitor multiplier, adaptive compensation is achieved by making the compensation capacitance to track the load current. The proposed pseudo-V2 control utilizes the output ripple to determine the duty cycle during load transient. Thus the overshoot/undershoot voltage and the transient recovery time are effectively reduced. Simulation results demonstrate the transient ripple is smaller than 50mV and the transient recovery time is shorter than 10μs for a 450mA load current step. The maximum power conversion efficiency is 94.6% at 1MHz switching frequency when input and output voltages are 5V and 1.8V, respectively.

Lower-power, high-linearity class-AB current-mode programmable gain amplifier

A novel class-AB implementation of a current-mode programmable gain amplifier (CPGA) including a current-mode DC offset cancellation loop is presented. The proposed CPGA is based on a current amplifier and provides a current gain in a range of 40 dB with a 1 dB step. The CPGA is characterized by a wide range of current gain variation, a lower power dissipation, and a small chip size. The proposed circuit is fabricated using a 0.18 μm CMOS technology. The CPGA draws a current of less than 2.52 mA from a 1.8 V supply while occupying an active area of 0.099 μm2. The measured results show an overall gain variation from 10 to 50 dB with a gain error of less than 0.40 dB. The OP1dB varies from 11.80 to 13.71 dBm, and the 3 dB bandwidth varies from 22.2 to 34.7 MHz over the whole gain range.

Integrated current-mode DC---DC boost converter with high-performance control circuit

In this paper, integrated BiCMOS amplifier and current-sensing circuits are introduced for high-performance DC---DC boost converter. By exploiting the advantage of BiCMOS technology, the high gain ...

Integrated current-mode DC–DC boost converter with high-performance control circuit

In this paper, integrated BiCMOS amplifier and current-sensing circuits are introduced for high-performance DC---DC boost converter. By exploiting the advantage of BiCMOS technology, the high gain amplifier and accurately sensed inductor current are obtained in the feedback control circuit. The proposed current-sensing circuit adopts a current-mirror instead of op-amplifier as a voltage follower so that it would reduce power consumption with a smaller chip-size. Bipolar transistor is also applied in the differential pair and current sources of the error amplifier to obtain a fast transient response. Frequency response shows the amplifier gain with the compensator affects significantly on the stability of the converter. The chip is fabricated in 0.35 µm 2-poly 4-metal BiCMOS process. The measurement shows that the current-sensing circuit can operate with accuracy of higher than 90 % at the frequency from 10 to 200 kHz and the transient time of the error amplifier is controlled within 10 µs. The converter with chip-size of 1 mm2 operates at the output voltage of 4.5---9 V with the frequency of 0.01---1 MHz.

Analysis and Comparison of Frequency Stabilization Loops in Self-Oscillating Current Mode DC–DC Converters

DC-DC converters, used in bidirectional applications such as battery/u-cap hybrid energy-storage systems, usually operate in current mode with a wide range of input and output voltages. Conventional current-mode control schemes, which requires adaptive slope compensation, are not attractive in these applications. In this paper, a class of self-oscillating hysteretic current-mode control (HCMC) schemes with frequency stabilization are analyzed and compared. Among them, the ripple HCMC scheme has the advantages of the inherent access to the average inductor current information, and inherent decoupling between the voltage and the frequency loops. The modeling and design procedure of two frequency regulation methods, namely the phase-locked loop (PLL) and delay-locked loop (DLL), are presented and compared in detail. The analysis is applicable to a range of inductive converters such as buck, boost, and buck-boost. HCMC implemented with a DLL is shown to not only offer comparable bandwidth compared to the PLL, but is also more robust against system parameter variations. The ripple HCMC controllers with PLL and DLL are implemented digitally, and the two schemes are verified experimentally on a 1 MHz 1-2.5 V to 5 V bidirectional boost converter prototype.

A current-mode DC—DC buck converter with adaptive zero compensation

To achieve fast transient response for a DC—DC buck converter, an adaptive zero compensation circuit is presented. The compensation resistance is dynamically adjusted according to the different output load conditions, and achieves an adequate system phase margin under the different conditions. An improved capacitor multiplier circuit is adopted to realize the minimized compensation capacitance size. In addition, analysis of the small-signal model shows the correctness of the mechanism of the proposed adaptive zero compensation technique. A current-mode DC—DC buck converter with the proposed structure has been implemented in a 0.35 μm CMOS process, and the die size is only 800 × 1040 μm2. The experimental results show that the transient undershoot/overshoot voltage and the recovery times do not exceed 40 mV and 30 μs for a load current variation from 100 mA to 1 A.

Fast transient DC–DC converter with adaptive compensation zero technique

This letter is to present an adaptive compensation zero circuit to achieve good transient response in current-mode DC---DC buck converter. The proposed structure introduces an adaptive resistance dynamically adjusted according to the different output load conditions, which achieves an adequate system phase margin. A monolithic DC---DC buck converter using the proposed structure was fabricated with 0.35 μm CMOS process. Measurement results show that the transient undershoot/overshoot voltage and the recovery time do not exceed 60 mV and 20 μs for a load current variation from 0 to 1 A.

A fast novel soft-start circuit for peak current-mode DC—DC buck converters

A fully integrated soft-start circuit for DC—DC buck converters is presented. The proposed high speed soft-start circuit is made of two sections: an overshoot suppression circuit and an inrush current suppression circuit. The overshoot suppression circuit is presented to control the input of the error amplifier to make output voltage limit increase in steps without using an external capacitor. A variable clock signal is adopted in the inrush current suppression circuit to increase the duty cycle of the system and suppress the inrush current. The DC—DC converter with the proposed soft-start circuit has been fabricated with a standard 0.13 μm CMOS process. Experimental results show that the proposed high speed soft-start circuit has achieved less than 50 μs start-up time. The inductor current and the output voltage increase smoothly over the whole load range.

Integrated on-chip 0.35 μm BiCMOS current-mode DC–DC buck converter

A current-mode DC–DC buck converter with a fully integrated power module is presented in this article. The converter is implemented using BiCMOS technology in amplifier and power MOSFET in a current sensor. The current sensor is realised by the power lateral double-diffused MOSFET with the aspect ratio much larger than that of a matched p-MOSFET. In addition, BiCMOS technology is applied in the error amplifier for an accurate current sensing and a fast transient response. The DC–DC converter is fabricated with 0.35 µm BiCMOS process. Experimental results show that the fully integrated converter operates at 1.3 MHz switching frequency with a supply voltage of 5 V. The output DC voltage is obtained as expected and the output ripple is controlled to be within 2% with a 30 µH off-chip inductor and 100 µF off-chip capacitor.

A Current-Mode DC–DC Buck Converter with Efficiency-Optimized Frequency Control and Reconfigurable Compensation

Large input voltage range and wide output current range are usually needed for dc-dc converters. For these input and output conditions, the converter's efficiency can be maximized by a proposed method, efficiency-optimized switching-frequency (EOF) control. The optimal switching frequency for maximizing the efficiency is generated by the low-complexity and low-power EOF generator. A reconfigurable compensator is developed for improving the load regulation and the transient response. A piecewise-linear current sensor (PLCS) is employed to reduce controller power loss without sacrificing the sensing accuracy. With the aforementioned three proposed methods, a monolithic current-mode dc-dc buck converter is implemented in a 0.35-μm 3.3-V CMOS process. The measured power-loss reductions and efficiency improvements achieve 16 and 15 mW, and 16% and 1%, both in light and heavy loads, respectively. The load regulation and the transient recovery time are improved by 40 mV and 12 μs, respectively, while the PLCS can reduce 3 mW of power loss. Compared with other published converters in 0.35-μm CMOS process, the implemented converter achieves a higher efficiency of 96.3% and smaller chip area of 0.97 mm.

Design of a hiccup mode over-current protection circuit for DC–DC switching converters

In the paper an improvement hiccup mode over-current protection circuit is proposed and successfully applied in a typical current-mode DC–DC switching converter. It greatly reduces the circuit power consumption in prolonged overload conditions and can provide smooth self-recovery once the overload condition is removed. By reducing the switching frequency and over-current threshold value, it further improves the effect of over-current protection. The power consumption and implementation area are minimized by digital control. By simulation and verification with HSPICE, the output average current is only 16.8% of the conventional over-current mode in continuous over-current conditions. The presented circuits can automatically recover with the maximum load (5A) when the overload is removed.

Design and implementation of adaptive slope compensation in current mode DC—DC converter

To improve the compensation for the inherent instability in a current mode converter, the adaptive slope compensation, giving attention to the problems of the traditional compensation on compensation accuracy, loading capability and turning jitter, is presented. Based on the analysis of current loop, by detecting the input and output voltage, converting the adaptive slope compensation current, the compensation of the current loop is optimized successfully. It can not only improve the compensation accuracy but also eliminate the over compensation, the turning jitter and the poor loading capability in the reported slope compensation. A power supply chip with adaptive slope compensation has been fabricated in a 0.35 μm CMOS process. The measurement results show that the chip starts up and operates steadily with the constant current limit under conditions of 5 V input voltage, from 10% to 100% duty cycle.