Current-mode Controlled Buck Converter Research Articles

A General Approach to Sampled-Data Modeling for Ripple-Based Control—Part II: Constant ON-Time and Constant OFF-Time Control

This part is the second part of this article and mainly presents the sampled-data modeling method for the dc–dc converters with the constant <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -time (COT) and constant <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> -time (COFT) controls. Compared with the constant frequency control in the first part, the duty cycle perturbation signal in the COT/COFT control is found to have two sets of narrow pulse signals in each switching period. Then, by establishing the relationship between the two sets of signals and using Shannon's sampling theorem, the transfer functions of the modulator and the loop gain are derived. Based on the theoretical results, the phenomenon that a current-mode constant <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> / <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> time controlled buck converter is stable at any duty cycle, and the instability of a voltage-mode constant <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> / <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> -time controlled buck converter with the smaller time constant of the output capacitor could be predicted. Moreover, the sampled-data modeling method is further extended to the digital control by taking a digitally current-mode controlled buck converter as an example. Simulation results are provided to confirm the validity of the proposed modeling method.

Enhanced Stability Caused by a One-Cycle Delay in a Digital Current-Mode Controlled Buck Converter

In the recent years, digital current mode control has gained popularity due to its technical benefits. However, designers face difficulties in controller design due to the delays associated with analog-to-digital (A/D) converter and controller computation. In software-based digital controller implementation, the cumulative delay of A/D conversion and controller computation may be comparable to the switching time period. This brief shows that the one-cycle delay in digital implementation in fact enhances the stability margin in a mixed-signal current mode controlled buck converter. By deriving a discrete-time model, we obtain the stability region in the parameter space and show that, if the controller gain is set within a specific range, the software-based implementation can achieve stable periodic (period-1) behavior without a ramp compensation even when the duty ratio exceeds 0.5. The theoretical results are validated with a buck converter prototype with a digital controller realized on an FPGA device.

Reduced-order Mapping and Design-oriented Instability for Constant On-time Current-mode Controlled Buck Converters with a PI Compensator

Reduced-order Mapping and Design-oriented Instability for Constant On-time Current-mode Controlled Buck Converters with a PI Compensator

Improved control strategy for photovoltaic emulator using resistance comparison method and binary search method

The current Resistance Comparison Method uses a fixed-step size in the iteration process to determine the operating point of the photovoltaic emulator. The weakness of the fixed-step size is the inaccuracy of the produced operating point and that it requires a high number of iterations to converge, which can burden the controller processor. This paper proposed a Resistance Comparison Method with an adaptable step size using the Binary Search Method for the photovoltaic emulator. The advantages of this control strategy are the fast operating point tracking capability, highly accurate operating point, and no readjustment is needed for the controller of the closed-loop converter system (robust). The simulation of the photovoltaic emulator system is conducted in the MATLAB/Simulink® using current-mode controlled buck converter with a Proportional-Integral compensator and a single diode photovoltaic model with a series resistor. The results obtained are compared to the conventional control strategy of the photovoltaic emulator. The proposed control strategy demonstrates an average of iteration convergence of 26 times better and 21 times more accurate compared to the conventional Resistance Comparison Method.

Dynamical effects of composite output capacitors on current‐mode controlled buck converter with constant current load

The discrete mapping model of current-mode controlled buck converter with constant current load, taking account of composite output capacitors (parallel connection of two different types of capacitor branches, i.e. electrolytic capacitors and ceramic capacitors), is established. Based on the model, dynamical effects of varying output capacitance and equivalent series resistance (ESR) are investigated by bifurcation behaviours. The period of low-frequency oscillation among coexisting fast-slow scale instability is derived by exploring the loci of eigenvalues, while the operating regions are estimated. Time-domain simulation and experimental waveforms are provided for verification of the theoretical analysis, indicating the existences of subharmonic oscillation and coexisting fast-slow scale instability in the converter with variation of output capacitance and ESR. Research results reveal that the low-frequency oscillation can be eventually eliminated due to a relatively large (or small) ESR and the capacitance in the same branch presents to identical tendency of dynamical effects on the converter. Moreover, the interaction effects between two parallel capacitor branches are demonstrated. It illustrates that the low-frequency oscillation can be removed with smaller (or larger) ESR or capacitance in one branch of the composite output capacitors while larger (or smaller) ESR or capacitance in the other branch.

Input Impedances of PWM DC-DC Converters: Unified Analysis and Application Example

The input impedances of pulse width modulated (PWM) dc-to-dc converters, which dictate the outcomes of the dynamic interaction between dc-to-dc converters and their source subsystem, are analyzed in a general and unified manner. The input impedances of three basic PWM dc-to-dc converters are derived with both voltage mode control and current mode control. This paper presents the analytical expressions of the 24 input impedances of three basic PWM dc-to-dc converters with the two different control schemes in a factorized time-constant form. It also provides a comprehensive reference for future dynamic interaction analyses requiring knowledge of the converters’ input impedances. The theoretical predictions of the paper are all supported by measurements on prototype dc-to-dc converters. The use of the presented results is demonstrated via a practical application example, which analyzes the small-signal dynamics of an input-filter coupled current-mode controlled buck converter. This elucidates the theoretical background for the previously-reported eccentric behavior of the converter.

A Unified Framework for Analysis and Design of a Digitally Current-Mode Controlled Buck Converter

Mixed-signal current-mode control (MCMC) implementation has been gaining popularity, because of the tuning flexibility using the digital voltage controller $G_{c}(z)$ along with the fast-changing analog current controller. Generally a continuous-time frequency-domain approach is adopted for the design of $G_{c}(z)$ ; however, this method often fails to capture sub-harmonic, more generally the fast-scale instability due to finite discretization effects. This paper derives approximate discrete-time models and proposes a unified framework to derive closed-form stability conditions and discrete-time small-signal models of a synchronous buck converter under MCMC. Considering the effects due to finite output-voltage sampling and the effective series resistance (ESR) of the output capacitor, the stability boundary in MCMC is found to be significantly restricted compared to its analog counterpart. Further, design methods are proposed to enhance stability boundary with improved transient performance by tuning the controller directly in the digital domain. A buck converter prototype is made, and the MCMC technique is realized using an FPGA device. Analytical predictions are verified experimentally.

Dynamics and stabilization of peak current-mode controlled buck converter with constant current load**Project supported by the National Natural Science Foundation of China (Grant No. 61371033), the Fok Ying-Tung Education Foundation for Young Teachers in the Higher Education Institutions of China (Grant No. 142027), the Sichuan Provincial Youth Science and Technology Fund, China (Grant Nos. 2014JQ0015 and 2013JQ0033), and the Fundamental

The discrete iterative map model of peak current-mode controlled buck converter with constant current load (CCL), containing the output voltage feedback and ramp compensation, is established in this paper. Based on this model the complex dynamics of this converter is investigated by analyzing bifurcation diagrams and the Lyapunov exponent spectrum. The effects of ramp compensation and output voltage feedback on the stability of the converter are investigated. Experimental results verify the simulation and theoretical analysis. The stability boundary and chaos boundary are obtained under the theoretical conditions of period-doubling bifurcation and border collision. It is found that there are four operation regions in the peak current-mode controlled buck converter with CCL due to period-doubling bifurcation and border-collision bifurcation. Research results indicate that ramp compensation can extend the stable operation range and transfer the operating mode, and output voltage feedback can eventually eliminate the coexisting fast-slow scale instability.

Control Design and Loop Gain Analysis of DC-to-DC Converters Intended for General Load Subsystems

DC-to-DC converters are usually intended for general applications where the load impedance characteristics are unknown or undefined. This paper establishes the control design procedures for DC-to-DC converters in the absence of any prior knowledge on their load impedance. The proposed control design can be universally adapted to all the DC-to-DC converters regardless of the impedance characteristics of their actual load. This paper also presents the loop gain analysis of the converter combined with an actual load whose impedance characteristics are only available afterward. A graphical analysis method is proposed, which enables us to predict the loop gain of the converter in the presence of an arbitrary load impedance. The validity of the analysis method is demonstrated using a current-mode controlled buck converter coupled with an inductive load, capacitive load, and converter load. Theoretical predictions are verified with both computer simulations and experimental measurements.

Control of sub‐harmonic oscillation in peak current mode buck converter with dynamic resonant perturbation

SummaryIn this paper, a dynamic resonant perturbation (DRP) method is proposed to control sub‐harmonic oscillation in a peak current mode controlled buck converter. Different from the traditional non‐feedback resonant parametric perturbation method, the proposed DRP method extracts an approximate sinusoidal control signal from the output voltage. The self‐stabilizing condition for the designed control signal is presented, and its analog circuit implementation is given as well. Furthermore, the system stability boundary is obtained by investigating the system eigenvalues, and the control parameter is effectively determined. The presented simulation and experiment results show that the proposed DRP method eliminates sub‐harmonic oscillation without sacrificing the peak value of the inductor current and features with a self‐stabilizing characteristic for external condition changes. Copyright © 2014 John Wiley &amp; Sons, Ltd.

COMPLEX DYNAMICS AND FAST-SLOW SCALE INSTABILITY IN CURRENT-MODE CONTROLLED BUCK CONVERTER WITH CONSTANT CURRENT LOAD

The complex dynamics and coexisting fast-slow scale instability in current-mode controlled buck converter with constant current load (CCL), operating in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM), are investigated in this paper. Via cycle-by-cycle computer simulation and experimental measurement of current-mode controlled buck converter with CCL, it is found that a unique fast-slow scale instability exists in the second-order switching converter. It is also found that a unique period-doubling accompanied by Neimark–Sacker bifurcation exists in this simple second-order converter, which is different from period-doubling or Neimark–Sacker bifurcations reported previously. Based on a nonlinear discrete-time model and the corresponding Jacobian, the effects of CCL and input voltage on the dynamics of current-mode controlled buck converter are investigated and verified theoretically. Fixed point analysis for slow-scale low-frequency oscillation is also given to verify the dynamics and the coexisting fast-slow scale instability.

Analysis of weight Lempel-Ziv complexity in piecewise smooth systems of DC-DC switching converters

A novel concept of switching block is presented via detecting the switching behavior of each switching period in piecewise smooth system of DC-DC switching converter, and logical arithmetic method of computer is used to obtain decimal system from binary system, so complex degree of the system during one switching period is quantized as switching block and the symbolic time sequence of the piece smooth system is established. Weight Lempel-Ziv (L-Z) complexity is derived based on the L-Z complexity and the symbolic time sequence, and the qualitative analysis of nonlinear and complex degree in piecewise smooth system from symbolic time sequence with single variable is carried out. The motion rule and the dynamics structure of the whole system are revealed. Finally, The present current mode controlled buck converter is studied as an example to establish symbolic time sequence and to illustrate the applications of weight L-Z complexity.

Fast-Scale and Slow-Scale Subharmonic Oscillation of Valley Current-Mode Controlled Buck Converter

A valley current-mode (VCM) controlled buck converter with current source load (CSI) has complex phenomena of fast-scale and slow-scale subharmonic oscillations. The piecewise smooth switching model of the VCM controlled buck converter with CSI is established. It is found that attractive regions of fast-scale and slow-scale subharmonic oscillations exist in the bifurcation diagram, and two tori exist in the corresponding Poincaré mapping. The research results by time-domain simulation indicate that U-type subharmonic oscillation (SO) constituted by SO and frequency-reduced subharmonic oscillation (FSO) exists in inductor current, and sine-type SO constituted by fast scale and low scale exists in output voltage respectively. Experimental results are given to verify the analysis and simulation results.

Exploration of Bifurcation and Chaos in Buck Converter Supplied From a Rectifier

The bifurcation phenomena in a current-mode controlled buck converter has been explored when the input of the converter is a rectifier having ripple in the output voltage instead of a regulated ideal dc power supply. A comparison between the two different input conditions shows a wide variation in most of the cases and it is difficult to predict the converter dynamics observing bifurcation diagram only. The mathematical model is developed in continuous conduction mode as well as in discontinuous conduction mode. The switching delay has been considered as its effect has great influence on bifurcation phenomena specially at higher switching frequency of the converter. The observed bifurcation phenomena have been verified experimentally.

Dynamical modeling and analysis of current mode controlled switching converter with ramp compensation

Buck, boost and buck-boost converters are three basic switching DC-DC converters. Current mode controlled switching DC-DC converters have two boundaries in a wide circuit parameters variation range. Based on the ramp up and ramp down slopes of the inductor current before and after the turn on of power switch for switching DC-DC converters, a unified model of the current mode controlled switching DC-DC converters with ramp compensation is established in this paper. Only three parameters appear in this model after dimensionless normalization, from which the dynamical behaviors of switching DC-DC converters in continuous conduction mode (CCM) and discontinuous conduction mode (DCM) can be effectively illustrated. By utilizing the proposed unified model, two orbit state shifting borderline equations are derived, from which three operation state regions namely the stable period-one region, CCM robust chaos region, and DCM weak chaos and strong intermittence region, of switching DC-DC converters can be determined. The two-dimensional parameter bifurcation diagrams of switching DC-DC converters and circuit experimental observations of current mode controlled buck converter verify the analysis results of the partitioning of operation state regions by two borderline equations.

Study on border collision and bifurcation of two-dimensional piecewise smooth systems in current mode controlled Buck converter

Border collision bifurcations have received much attention in recent years. A class of piecewise smooth maps with two border and three zones is derived to describe the dynamics of a current-programmed Buck converter operating in a discontinuous mode. The numerical simulation is carried out and the bifurcation diagrams with the reference current as a parameter are obtained. Then, a concrete analysis of the stable existence condition of the fixed point is made, and the structure of bifurcation diagrams and a change in operation mode of the converter at the border collision point are studied. Finally, simulation and experimental results show that the theoretical analysis is correct.

EXPERIMENTAL VERIFICATION OF BORDER COLLISION BIFURCATION DUE TO MODE TRANSITION IN A CURRENT MODE CONTROLLED BUCK CONVERTER

The bifurcation phenomena occurring in a current mode controlled buck converter when it shifts from continuous conduction mode (CCM) to discontinuous conduction mode (DCM) have been reported. A sampled data model has been developed considering CCM as well as DCM. The bifurcation phenomena observed in such converters have been verified experimentally.

An improved sampled-data current-mode-control model which explains the effects of control delay

A new sampled-data model for the current-mode controlled buck converter includes for the first time the effects of delay in the pulse-width-modulator (PWM). Modified z-transforms are used in this new model for constant frequency trailing-edge modulation. Realistic amounts of delay are found to be particularly significant when the buck converter is operating in the continuous conduction mode near the discontinuous conduction mode boundary. The new model is used to predict the loop gain measurements obtained with the and with conventional measurement techniques. It is shown that conventional loop gain measurement techniques are insufficient to measure the loop gain in this region of operation. It is also shown that the digital modulator can add a significant amount of delay, thereby altering the loop gain of the circuit being measured. Unlike the case of a continuous system, PWM delay is found to significantly alter the low-frequency loop gain magnitude of this sampled-data system. The new model predicts the boundary condition for sub-harmonic instability, and reduces to Ridley's current-mode control model for the case of zero delay. Experimental corroboration is presented.

Novel control design for the buck converter

A novel control design approach for average current-mode controlled buck converters is presented. The buck converter large-signal averaged model is shown to be easily large-signal linearisable. The linear model is then examined as a multivariable system with no inner and outer loops, using both the state-space and frequency domain descriptions. Transfer functions of the system are derived as a function of the desired closed-loop poles, simplifying the design procedure and bringing forward all the important characteristics of the closed-loop system. Several advantages can be gained by the use of capacitor current instead of inductor current feedback. Theoretical analysis is applied and confirmed with simulation and experimental results on a 250 W prototype. The proposed approach can be used with all small-signal linear models of DC–DC converters, offering simplicity and a better insight on system characteristics.