Current Mirror Mismatch Research Articles

A 3.0-V 4.2-μA 2.23-ppm/°C BGR with cross-connected NPNs and base-current compensation

This paper presents a high-precision, low-power bandgap voltage reference with a 3.0 V output voltage suitable for battery-management systems. Compared to Brokaw's type bandgap references (BGRs), Cross-connected NPN transistors facilitate higher output voltages without the necessity of operational amplifiers and are unaffected by the current-mirror mismatch. Base-current compensation is proposed to address the effect of base current on voltage output temperature characteristics at low power consumption. A piecewise exponential curvature correction stains high-order compensation for the nonlinear characteristic of base-emitter voltage. Experimental results of the proposed BGR implemented in a 0.18-μm Bipolar-CMOS-DMOS (BCD) process demonstrate that the temperature coefficient is 2.23 ppm/°C over the range of −40 °C–120 °C. The line regulation is 0.2 mV/V at a 5–6 V supply voltage with a supply current of only 4.2 μA. The die area of the fabricated BGR is 0.105 mm2.

A New Digital to Analog Converter Based on Low-Offset Bandgap Reference

This paper presents a new 12-bit digital to analog converter (DAC) circuit based on a low-offset bandgap reference (BGR) circuit with two cascade transistor structure and two self-contained feedback low-offset operational amplifiers to reduce the effects of offset operational amplifier voltage effect on the reference voltage, PMOS current-mirror mismatch, and its channel modulation. A Start-Up circuit with self-bias current architecture and multipoint voltage monitoring is employed to keep the BGR circuit working properly. Finally, a dual-resistor ladder DAC-Core circuit is used to generate an accuracy DAC output signal to the buffer operational amplifier. The proposed circuit was fabricated in CSMC 0.5 μm 5 V 1P4M process. The measured differential nonlinearity (DNL) of the output voltages is less than 0.45 LSB and integral nonlinearity (INL) less than 1.5 LSB at room temperature, consuming only 3.5 mW from a 5 V supply voltage. The DNL and INL at −55°C and 125°C are presented as well together with the discussion of possibility of improving the DNL and INL accuracy in future design.

Inspection of the Current-Mirror Mismatch by Secondary Electron Potential Contrast With In Situ Nanoprobe Biasing

The mismatch mechanism in a current mirror consisting of laterally diffused p-channel MOS (LDPMOS) technology was investigated using a scanning electron microscope (SEM) with in situ nanoprobing. The electrical measurement found a saturation current mismatch of 52 μA between the LDPMOS transistors. Furthermore, the proposed inspection identified successfully 0.4-μm p-well layer misalignment, which was the root cause of the mismatch. This letter demonstrates that an in situ nanoprobing system is a powerful tool for enhancing p-well dopant contrast in a SEM, analyzing site-specific failures, and studying device physics under a dynamic scope.

Adaptive log domain filters for system identification using floating gate transistors

We describe an adaptive log domain filter with integrated learning rules for model reference estimation. The system is a first-order low pass filter implemented using multiple input floating gate transistors operating in subthreshold to realize on-line learning of gain and cut-off frequency. We use adaptive dynamical system theory to derive robust control laws for gain and cut-off frequency adaptation in a system identification task. Simulation results show that convergence is slower using simplified control laws but still occurs within milliseconds. Experimental results confirm that the estimated gain and cut-off frequency track the parameters of the reference filter. The adaptive log domain filter has measured power consumption of 33 μW. During operation, deterministic errors are introduced by mismatch within the analog circuit implementation. An analysis is presented which attributes the errors to current mirror mismatch.