Current Memory Cell Research Articles

A Fully Differential CMOS Current Memory Cell for Space-Embedded Analog-to-Digital Converters

This paper presents a radiation-hardened high-resolution current memory cell (CMC) that can be used to implement current-mode analog-to-digital converters (ADCs) for space-embedded, charge-coupled device processors. This CMC is based on a fully differential structure and on the Miller effect to reduce charge-injection errors. Using a commercial 0.35-μm 3.3-V complementary metal-oxide-semiconductor (CMOS) process, the radiation tolerance of this CMC has been enhanced by designing enclosed n-channel MOS transistors, using p-channel MOS switches only, and introducing guard rings wherever necessary. Results show that the CMC accuracy is 10 bits and that its estimated linearity error is &3x000B1;50 nA for a [-200 μA; 200 μA] dynamic input current range. Experimental results point out that signal-dependent charge injections are divided 23 times at least, which improves the CMC accuracy by approximately 4 bits. The measured acquisition time for a 200-μA input step transition to achieve a 10-bit settling accuracy is 50 ns. The active chip area and the power consumption of the proposed CMC are 0.042 mm 2 and 6 mW, respectively.

A Novel Time-Series Memory Auto-Encoder With Sequentially Updated Reconstructions for Remaining Useful Life Prediction.

One of the significant tasks in remaining useful life (RUL) prediction is to find a good health indicator (HI) that can effectively represent the degradation process of a system. However, it is difficult for traditional data-driven methods to construct accurate HIs due to their incomprehensive consideration of temporal dependencies within the monitoring data, especially for aeroengines working under nonstationary operating conditions (OCs). Aiming at this problem, this article develops a novel unsupervised deep neural network, the so-called times series memory auto-encoder with sequentially updated reconstructions (SUR-TSMAE) to improve the accuracy of extracted HIs, which directly takes the multidimensional time series as input to simultaneously achieve feature extraction from both feature-dimension and time-dimension. Further, to make full use of the temporal dependencies, a novel long-short time memory with sequentially updated reconstructions (SUR-LSTM), which uses the errors not only from the current memory cell but also from subsequent memory cells to update the output layer's weight of the current memory cell, is developed to act as the reconstructed layer in the SUR-TSMAE. The use of SUR-LSTM can help the SUR-TSMAE rapidly reconstruct the input time series with higher precision. Experimental results on a public dataset demonstrate the outstanding performance of SUR-TSMAE in comparison with some existing methods.

Stability of polarisation vortex in ferroelectric nanofilm under stress or curled electric field

ABSTRACT Polarisation vortex structures in ferroelectric materials are being considered as a promising alternative to current memory cells due to the merit of high storage density. However, ferroelectric storage devices would inevitably be affected by external loads. When an applied mechanical or electrical load reaches its critical value, it could cause the loss of stored data because the polarisation vortex loses the stability. Some phase field simulations were conducted to investigate the stability of the polarisation vortex under different stresses or curled electric fields. The results show that the polarisation vortex structure has the strongest resistance to a tensile stress, followed by a compressive stress, but the weakest to a curled electric field. The temperature sensitivity of the polarisation vortex structure to resist different loads is also significantly different. The temperature sensitivity is the strongest for the curled electric field, followed by for the tensile stress, but the weakest for the compressive stress. This work would be helpful for tuning polarisation vortex and designing ferroelectric storage devices in specific working environments.

Rewritable ferroelectric vortex pairs in BiFeO3

Ferroelectric vortex in multiferroic materials has been considered as a promising alternative to current memory cells for the merit of high storage density. However, the formation of regular natural ferroelectric vortex is difficult, restricting the achievement of vortex memory device. Here, we demonstrated the creation of ferroelectric vortex-antivortex pairs in BiFeO3 thin films by using local electric field. The evolution of the polar vortex structure is studied by piezoresponse force microscopy at nanoscale. The results reveal that the patterns and stability of vortex structures are sensitive to the poling position. Consecutive writing and erasing processes cause no influence on the original domain configuration. The Z4 proper coloring vortex-antivortex network is then analyzed by graph theory, which verifies the rationality of artificial vortex-antivortex pairs. This study paves a foundation for artificial regulation of vortex, which provides a possible pathway for the design and realization of non-volatile vortex memory devices and logical devices.

A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process.

This paper presents a 4 × VDD neuro-stimulator in a 0.18- μm 1.8 V/3.3 V CMOS process. The self-adaption bias technique and stacked MOS configuration are used to prevent transistors from the electrical overstress and gate-oxide reliability issue. A high-voltage-tolerant level shifter with power-on protection is used to drive the neuro-stimulator The reliability measurement of up to 100 million periodic cycles with 3000- μA biphasic stimulations in 12-V power supply has verified that the proposed neuro-stimulator is robust. Precise charge balance is achieved by using a novel current memory cell with the dual calibration loops and leakage current compensation. The charge mismatch is down to 0.25% over all the stimulus current ranges (200-300 μA) The residual average dc current is less than 6.6 nA after shorting operation.

A Hybrid Verilog-A and Equation-defined Subcircuit Approach to MOS Switched Current Analog Cell Simulation

Conventional modeling and simulation of two-phase switched current MOS-integrated circuits is normally undertaken at semiconductor device level. This allows primary and secondary circuit effects to be studied and characterized. However, with the growing complexity of these circuits, transient domain simulation times can become prohibitively long, restricting the size of circuit that can be easily investigated. Measurable reductions in transient simulation run times can be achieved by modeling part, or all, of a switched current design as a macromodel. This paper introduces a hybrid approach to MOS switched current circuit modeling that combines the primary features of compact device modeling with functional circuit macromodeling. To illustrate the proposed hybrid modeling procedure the properties, and simulation model, of a MOS switched current analog memory cell are described. The material presented also demonstrates how recent trends in “Quite universal circuit simulator” (QUCS) technology promote embedded Verilog-A models and equation-defined subcircuits as integral elements in mixed-mode circuit and system design.

Compiling a Conductivity Matrix of a Switched Currents Circuits by Means of Two-Graphs

The paper deals with the possibility to use two-graphs to compile a conductivity matrix describing a circuit with switched currents in two-phase switching. It demonstrates the compilation of a matrix both by using a real graph and by using a graph expressed in the form of a table. The described method appears somewhat less toilsome than the method of compiling by modelling current memory cell.

Improving Switched Current Sigma Delta Modulators' Performances via the Particle Swarm Optimization Technique

This paper presents the optimal design of a switched current sigma delta modulator. The Multi-objective Particle Swarm Optimization technique is adopted to optimize performances of the embryonic cell forming the modulator, that is, a class AB grounded gate switched current memory cell. The embryonic cell was optimized regarding to its main performances such as sampling frequency and signal to noise ratio. The optimized memory cell was used to design the switched current modulator which operates at a 100 MHz sampling frequency and the output signal spectrum presents a 45.75 dB signal to noise ratio.

A novel Alienor-based heuristic for the optimal design of analog circuits

A heuristic for solving (non-linear and constrained) analog optimization problems is proposed. The method is based on an approximation of multi-variable multi-objective problems by a mono-objective problem of one variable: the Alienor technique and a normalization technique are used for this purpose. Application to the optimal design of an inverted CMOS current conveyor and a class AB grounded gate switched current memory cell are given.

Low-voltage, low-power, low switching error, class-AB switched current memory cell

A class-AB switched current memory cell is proposed. The circuit decomposes the input signal into two components by a low-voltage class-AB current splitter and subsequently processes the individual signals by two low switching error class-A memory cells. As a consequence, the output current obtained by recombination of the separated signals can be higher than the bias current and features low error. Simulation results confirm that, for a 0.75V supply, a 5MS/s sampling frequency, and a 500 kHz sinusoidal input current having 400% modulation index, the proposed memory provides less than −45 dB THD output current with very low switching error.

0.75 V micro-power SI memory cell with feedthrough error reduction

A simple technique to realise a switched current memory cell operating from low supply voltage (0.75 V) with clock-feedthough (CFT) error reduction is presented. Unlike previous techniques that try to minimise current error by compensation at the output, this technique prevents the occurrence of current error by removing the feedthrough voltage from the input port of the memory transistor directly. As a result, the CFT error current at the output is almost completely eliminated employing a simple and compact circuit structure. Simulation results are given, showing good agreement to the theory.

Low-Power Switched Current Memory Cell with CMOS-Type Configuration

This letter presents a low-power switched current (SI) memory cell with CMOS-type configuration. By combining nMOS and pMOS in the SI memory cell and using a polarity discrimination circuit, we design a CMOS-type SI memory cell which eliminates the quiescent current in the SI memory cell. The simulation result shows that the CMOS-type SI memory cell consumes less power than the conventional class-AB memory cell.

Current Mode Monolithic Active Pixel Sensor With Correlated Double Sampling forCharged Particle Detection

A monolithic active pixel sensor operating in current mode for charged particle detection is described. The sensing element in each pixel is an n-well/p-sub diode with a PMOS transistor integrated in an n-well. The drop of the n-well potential from the collection of charge modulates the transistor channel current. Each pixel features two current mode memory cells. The subtraction of distant-in-time samples frees the signal of fixed pattern noise (FPN) and of the correlated low-frequency temporal noise components, resulting in extraction of the particle footprint. The subtraction circuits are placed at each column end. A transimpedance amplifier, integrating in sequence two current samples and subtracting the results in an arithmetic operation, was adopted. The integrated version of the transimpedance amplifier, designed with a maximized conversion gain, is burdened by a risk of an early saturation, imperiling its operation, if the dispersions of the dc current component are too big. The degree of dispersions could not be estimated during the design. Some number of columns is available as a backup with the direct current readout. An external realization of the subtracting circuit, based on the same principle, is used to process direct output columns. The concept of the data acquisition setup developed, the tested performance of an array of cells, and the processing circuitry are described

Resistance Switching In Ferroelectric Materials

AbstractA ferroelectric crystal with perovskite structure such as PbZr1−xTixO3 (PZT), SrBi2Ta2O9 (SBT), Bi3La1−xTixO12 (BLT) and non-perovskite structure such as Pb3Ge5O11 (PGO) have two polarization states, which can generate two resistance states: high resistance and low resistance states. These properties can be used for resistance random access memory applications (RRAM). When a ferroelectric capacitor is polarized an internal electric field opposite polarity to the external applied field is generated. As a result there is a large resistance change at a given bias voltage between the two polarization states of the capacitor. It is the purpose of this paper to show that the ferroelectric capacitor may be used as a current memory cell of non-destructive readout (NDRO) non-volatile Random Access Memory array. It will also be shown that each current sensing ferroelectric memory cell stores two bits of memory information and exhibits long memory retention and excellent endurance properties.

Optimizing performances of switched current memory cells through a heuristic

Optimally designing switched current (SI) memory cells is a hard task. In addition, it is usually limited to the design of ideal cells. Thus, in this paper we deal with optimizing these cells and precisely real ones using a heuristic. Since SI class AB grounded gate memory cells are well known to be improved cells, we applied the proposed heuristic to design this kind of cells. Also, besides maximizing performances and minimizing famous error sources, we focus on optimally sizing transistors forming switches and bias sources. The optimization procedure, developed with help of C++ software, allows automatic design of the cell. It is also highlighted in the followings.

A Low-Power Current Mode Fuzzy-ART Cell

This paper presents a very large scale integration (VLSI) implementation of a low-power current-mode fuzzy-adaptive resonance theory (ART) cell. The cell is based on a compact new current source multibit memory cell with online learning capability. A small prototype of the designed cell and its peripheral block has been fabricated in the AustriaMicroSystems (AMS)-0.35-microm technology. The cell occupies a total area of 44 x 34 microm2 and consumes a maximum current of 22 nA.

Development of a prototype module for a DEPFET pixel vertex detector for a linear collider

For operation at a linear collider the excellent noise performance of depleted field effect transistor (DEPFET) pixels allows building very thin detectors with high spatial resolution and low power consumption. However, high readout speeds of 50 MHz line rate and 20 kHz for the full detector must be reached. A prototype system is presented, using a new DEPFET pixel matrix (128 /spl times/ 64 pixels), fast steering chips (Switcher II) for row wise operation and a fast current based readout chip (CURO II). The sensors with small linear DEPFET pixels (22/spl times/36 /spl mu/m/sup 2/) are optimized for fast readout and high spatial resolution. Measurements show that the complete removal of the accumulated signal charge from the internal gate (complete clear), which is fundamental for the foreseen readout mode, is feasible. The current based readout chip CUROII, containing current memory cells, pedestal subtraction and on chip zero suppression for a triggerless operation has been fabricated and tested. First results of a full prototype system are presented.

A low-power and compact CDMA matched filter based on switched-current technology

A low-power and compact code-division multiple-access (CDMA) matched filter has been developed using the switched-current technology. On-chip V-I and I-V converters featuring moderate linear characteristics have been developed for the chip. The low-power operation has been achieved by the sub-block architecture, which reduced the current flowing in current-memory cells. A low-power clock-on-demand shift register has also been developed. The 256-chip matched filter fabricated in a 0.35-/spl mu/m technology demonstrated the power dissipation of 1.95 mW at the chip rate of 8 Mchip/s under 2-V power supply. The chip occupies the area of 0.54 mm/sup 2/.

New results on DEPFET pixel detectors for radiation imaging and high energy particle detection

DEPFET pixel detectors are unique devices in terms of energy and spatial resolution because very low noise operation can be obtained (ENC=2.2e/sup -/ at room temperature) by implementing the amplifying transistor in the pixel cell itself. Full DEPFET pixel matrices have been built and operated for autoradiographical imaging with imaging resolutions of 4.3/spl plusmn/0.8 /spl mu/m at 22 keV. For applications in low energy X-ray astronomy the high energy resolution of DEPFET detectors is attractive. For particle physics, DEPFET pixels are interesting as low mass detectors with high spatial resolution. For a linear collider detector the readout must be very fast. New readout chips have been designed and produced for the development of a DEPFET module for a pixel detector at the proposed TESLA collider, containing 520/spl times/4000 pixels, with 50 MHz line rate and 25 kHz frame rate. The circuitry contains current memory cells and current hit scanners for fast pedestal subtraction and sparsified readout. The imaging performance of DEPFET devices as well as present achievements toward a DEPFET vertex detector for a linear collider are presented.

Ferroelectric field-effect transistor with a SrRuxTi1−xO3 channel

A ferroelectric field-effect transistor with a SrRuxTi1−xO3 solid-solution channel layer and a lead zirconate titanate gate oxide has been fabricated. The remnant polarization of the ferroelectric yields two states at 0 V, which produce a relative change in channel resistance (ΔR/R) of 75% and a coercivity of 3 V. The channel has sufficient off-state free carrier concentration to provide sufficient balancing charge for ferroelectric stability. The device was subjected to more than 1010 read-write cycles with no degradation. This nonvolatile device offers the possibility of a nondestructive, current sense memory cell with good retention properties.