Current-limiting Inductor Research Articles

A hybrid multi-port HVDC circuit breaker that improves interruption and reset time through shared energy dissipation and fault current regeneration

This paper proposes a Hybrid Multi-Port DC Circuit Breaker (HMPDCCB) design that addresses the limitations of existing hybrid DC circuit breakers (HDCCBs), such as high cost, complexity, and slow response to high fault current and voltage demands. The HMPDCCB is based on a common breaker, energy dissipation, and regeneration branch for all connected HVDC lines, reducing interruption time to 1.8 milliseconds. It effectively manages fault energy through Insulated Gate Bipolar Transistors (IGBTs) of the main breaker branch with parallel surge arrester, reducing energy losses and enhancing power system efficiency. The HMPDCCB provides selective protection for all connected DC lines at a lower investment cost and incorporates current-limiting inductors (CLIs) to slow the rise of fault currents. The proposed HMPDCCB has been rigorously modelled and simulated using MATLAB Simulink®/Simpowersystems, and the simulations show that it achieves a fault current interruption time of 1.8 milliseconds and a reset time of fewer than 3 milliseconds, outperforming existing models.

DC circuit breaker: A topology with regenerative current breaking capability for DC microgrid applications

The modern DC grid is predominantly inductive due to several factors, including line inductance, and the use of current-limiting inductors to control fault current rising rates. These network inductances store a significant amount of energy during regular operation, which is either dissipated or freewheeled to ensure safe current breaking. This research article proposed a highly efficient bidirectional DC circuit breaker topology that not only provides safe current breaking but also effectively recovers the post-current breaking energy from the network’s inductance instead of dissipation. An extensive simulation investigation is performed in PSIM software to test the breaker capability for a 400V/400A DC system and the laboratory-scale 48V/1A experimental setup has been developed and employed for further validation purposes.

Non-unit protection method for MMC-HVDC grids based on selective drop rate of voltage traveling waves

Fast, sensitive, and selective protection principles are one of the major challenges in the feasibility of modular multi-terminal (MMC) high voltage direct current (HVDC) grids. Rate of change of voltage (ROCOV) and transient-based solutions are the traditional and widely accepted protection principles. Despite the speed and practicality of these solutions, they generally suffer from sensitivity and selectivity issues, particularly when dealing with high-resistance faults and low-size current limiting inductors (CLIs). To improve upon these methods, this paper proposes a new primary protection method that utilizes a selective drop rate of fault-generated voltage traveling waves (TW) to detect internal DC line faults. This is achieved by a comprehensive analysis of the line-mode fault-generated voltage (LFGV) under various internal and external fault scenarios. As the key fault characteristics, the proposed method exploits the minimum points of initial LFGV and the corresponding time to form the basis of the proposed protection method. The effectiveness of this approach is evaluated using a four-terminal MMC-HVDC grid in PSCAD/EMTDC. Compared to ROCOV and transient-based solutions, the proposed method identifies internal faults up to 1250 Ω with fast response, while maintaining its practicality and independence to CLI size.

Parameter Optimization Design of the Commutation Circuit of a Hybrid DC-Current-Limiting Circuit Breaker

Aimed at the optimization design of the parameters of the commutation circuit of a hybrid DC-current-limiting circuit breaker (HDCCLCB), a parameter selection model considering the short-time withstand of the thyristor and the volume of the commutation circuit is proposed by simplifying the object, and the commutation circuit parameters were preliminarily obtained. In order to verify the correctness of the method of selecting the commutation circuit parameters, the circuit simulation model of the HDCCLCB was built. The experimental platform was built, and the breaking experiment was completed under the fault condition with the current rising rate of 20 A/μs. The correctness of the simulation model and parameter design method was verified by comparing the circuit model simulation results with the experimental results. In order to further optimize the parameters of the commutation circuit, a mathematical model for optimization design was established. Taking the maximum critical breakdown voltage under unit capacitance energy as the objective function, the arcing time before commutating and the current-limiting inductance and capacitance are enumerated to obtain the optimized commutation circuit parameters. By comparing this result with the result of the preliminary design, the objective function is improved by 20.7%, laying a solid foundation for further research and the development of current-limiting circuit breakers for medium-voltage DC systems.

Admittance Criterion of Medium-Voltage DC Distribution Power System and Corresponding Small Signal Stability Analysis

Aiming at the stability of a medium-voltage DC network based on a modular multilevel converter (MMC), this paper proposes an admittance stability criterion considering the influence of current-limiting inductors at the medium voltage side, which prevents the complex products and matrix calculations of traditional criteria. The DC admittance model DC transformers (DCTs) under different working modes are then established based on Thevenin/Norton equivalent circuit methods to analyze the stability of the DC system based on the proposed admittance stability criterion, which proves that the voltage resonance problem at the medium voltage side can be improved by adding active damping control strategies on DCTs also proves the effectiveness of the proposed stability criterion. The time-domain simulation and the hardware-in-loop simulation are then built in PLECS and RT Box to further verify the correctness of the system stability analysis and the effectiveness of the proposed admittance criterion, which provides a theoretical basis and technical reserve for the stable operation of the DC distribution power system.

Multiport Current-Limiting Hybrid DC Circuit Breaker for MTdc Grids

The coordination configuration of current-limiting inductors (CLIs) and hybrid dc circuit breakers (HCBs) is currently the most commonly used fault handling method to ensure fault ride-through of multi-terminal dc (MTdc) grids after the dc-side fault occurs. However, the high cost of HCB limits its large-scale application. In addition, the installation of the large CLIs will adversely affect the HCB performance, such as extending the fault current interruption time and increasing the energy dissipation pressure of the arrester. To solve these problems, a multiport current-limiting hybrid dc circuit breaker (MCL-HCB) is proposed in this paper. Compared with the typical HCBs, the MCL-HCB can achieve full selective protection of all connected dc lines with significantly reduced investment costs. Besides, it can suppress the rising speed of the fault current by embedded CLIs, while eliminating their negative impacts on the fault current interruption. The feasibility and superiority of the proposed MCL-HCB are verified by simulations in the PSCAD/EMTDC software and experiments in the scaled-down experimental setup. Besides, the performance comparison between the MCL-HCB and existing solutions is elaborated.

Improved Integrated Hybrid DC Circuit Breaker for MTDC Grid Protection

The current-limiting inductors are usually installed in the multi-terminal dc grid to limit the fault current rising speed. However, they will increase the energy dissipation pressure and fault isolation time of the dc circuit breaker, which puts forward higher requirements on the capacity of arresters in hybrid dc circuit breaker and the heat dissipation of grid equipment. Therefore, an improved integrated hybrid dc circuit breaker is proposed in this brief for applications in the multi-terminal dc grid. Compared with the fault isolation solution based on existing integrated hybrid dc circuit breakers, the proposed breaker has slightly higher cost of semiconductor switches but significantly reduced arrester capacity requirement and faster fault isolation speed by bypassing the inductance components. Extensive electromagnetic simulations and physical experiments verify the effectiveness of the proposed device.

A hybrid circuit breaker with fault current limiter circuit in a VSC-HVDC application

A conventional hybrid circuit breaker (HCB) is used to protect a voltage source converter-based high voltage direct current transmission system (VSC-HVDC) from a short circuit fault. With the increased converter capacity, the DC protection equipment also requires a regular upgrade. This paper adopts a novel type of HCB with a fault current limiter circuit (FCLC), and focuses on the responses of voltage and current during DC faults, which are associated with parameter selection. PSCAD/EMTDC based simulation of a three-terminal VSC-HVDC system confirms the effectiveness and value of HCB with FCLC, by using an equivalent circuit modelling approach. Laboratory experimental tests validate the simulation results. The peak fault current is reduced according to the current limiting inductor (CLI) increase, and can be isolated more quickly. By adopting parallel metal oxide arrester (MOA) with the main branch of HCB, voltage stresses across the breaker components decrease during transient and continuous operation, and less energy needs to be dissipated by the MOA. The remnant current for all cases is transmitted to power dissipating resistor (PDR) in the final stage, and the fault current is reduced to the lowest possible value. When the current from the main branch is transferred to the FCLC branch, transient voltage spikes occur, while smaller PDR is required to absorb current in the final stage.

Design and Implementation of Novel Fault Ride through Circuitry and Control for Grid-Connected PV System

This paper provides a comparison of a designed method of a fault ride through (FRT) circuit, i.e., switch-type fault current limiter (STFCL) and bridge-type fault current limiter (BFCL), to optimize the electrical parameters of grid-connected solar systems (PVSs) under asymmetric single line-to-ground fault and symmetric three-phase fault. The main differences between switch- and bridge-type fault current limiters is the electric component devices such as the bridge rectifier, snubber capacitor, energy absorption bypass and current-limiting inductors. In addition, the designed FRT performance with the inverter control are analyzed in-depth, e.g., a well-adjusted proportional integral (PI) and proposed steepest descent (SD) controller are compared in the fault condition. To compare the proposed method with the conventional method, the AC power and voltage on a common coupling point (PCC) and DC link voltage of the PV system are analyzed with a MATLAB/Simulink model of a 100 kW three-phase grid-connected photovoltaic system. The simulation results of the proposed FRT circuit and SD controller verify the stability improvement and vibration-free and fast and robust responses of electrical parameters on both PV grid sides during asymmetric disturbances.

An AC Fault Ride Through Method for MMC-HVDC System in Offshore Applications Including DC Current-Limiting Inductors

The current-limiting inductors (CLIs) are commonly used to suppress DC fault current to safely trip DC circuit breakers in MMC-HVDC systems, but it significantly jeopardizes DC dynamics and causes instantaneous power mismatch between AC and DC sides of islanded rectifier station (RS), exposing MMC internal states to large disturbance. This paper firstly provides a detailed analysis of the influence of CLIs on AC fault, establishes RS mathematical representation including AC side dynamic, and reveals the mechanism of DC voltage oscillation, modulation saturation and PCC waveform distortion. The analysis shows that the AC and DC fault characteristics are decoupled under unsaturated AC modulation, but coupled under excessively low submodule capacitor voltage, where AC modulation is saturated and PCC waveforms are distorted. To solve this issue, a novel RS AC fault ride through method for MMC-HVDC system with CLIs is proposed to stabilize RS DC voltage, desaturate AC modulation and decouple fault characteristics by regulating the zero-sequence modulation of circulating current suppression. In addition, a current reference disturbance and an AC energy dissipation device coordinated control are designed, which adaptively recovers the submodule capacitor voltage. Finally, the feasibility of the proposed method is verified by simulation results.

Bridge-Type Multiport Fault Current Limiter for Applications in MTdc Grids

Since the dc-side fault in the multiterminal dc grid propagates extremely fast, the fault current limiter (FCL) is essential to achieve fault ride-through of the healthy network. Current-limiting inductors (CLIs) are currently the most commonly used FCLs in projects that have been built, are under construction, or are planned. The CLIs can be designed based on the system requirements, such as converter fault ride-through and dc circuit breaker (DCCB) interrupting capacity. Unfortunately, the installation of CLIs has negative impacts on the system transient response and operational stability, the fault isolation speed and energy dissipation of DCCBs. To solve these problems, an economical bridge-type multiport fault current limiter (BT-MFCL) is proposed in this article, which can be installed at the dc bus with multiple dc lines connected and can cooperate with the existing DCCBs. The BT-MFCL is composed of a CLI on each port and a shared energy dissipation circuit (EDC). The fault current can be limited by the embedded CLIs in the BT-MFCL without a time delay, while the EDC can eliminate the negative influences of CLIs. Extensive simulations and experiments have verified the effectiveness of the BT-MFCL. Besides, the performance comparison of the BT-MFCL with existing solutions is elaborated.

Stability Analysis of High-Frequency Interactions Between a Converter and HVDC Grid Resonances

This paper analyzes high-frequency interactions between a Modular Multilevel Converter (MMC) and High Voltage Direct Current (HVDC) grid resonances by studying their effect on the system stability. The recent appearance of converter-related instabilities due to high-frequency oscillations at the converter's ac side raises concerns about whether similar interactions can also take place at its dc side. To determine the risks imposed by such interactions within an HVDC grid, this paper assesses the impact of the MMC internal dynamics and dc system resonances on the stability using an analytical impedance-based method. The effect of fault current-limiting inductors, grid topology changes and transmission line length is investigated, indicating that these parameters considerably influence the electromagnetic characteristics of the HVDC grid and consequently the system stability. Furthermore, a sensitivity analysis of the MMC internal controller dynamics on the converter's non-passivity, causing the instability, is performed.

Design of lossless snubber circuit for phase-shifted full-bridge converter

In the phase-shifted full-bridge circuit, the voltage spike caused by the hard turn-off of the switch tube increases the voltage stress of the switching device. Due to the existence of energy-consuming components such as resistance in the traditional absorption circuit, the efficiency is not always high. Based on the RCD snubber circuit, a low-loss absorption circuit is designed in this paper. This circuit absorbs voltage spikes through an absorption capacitor, and then slowly releases energy through an oscillating circuit consisting of current-limiting inductance, stray inductance, and absorption capacitance. The current-limiting inductance reduces the current stress of the blocking diode effectively, which can be achieved with the absorption not being affected and the power loss being reduced. Finally, the absorption effect and energy loss of the new low-loss absorption circuit and the commonly used RCD circuit were simulated and compared in PSpice software, and verified its feasibility.

Modeling of the DC Inductive Superconducting Fault Current Limiter

DC fault current limiter is an important device for the dc system, because the action speed of the existing selective protection cannot match the dc fault developing speed. Due to its excellent capacity on limiting dc fault rising speed, the analyses of dc inductive type superconducting fault current limiter (I-SFCL) are attracting more attention. In this paper, a modeling method for dc I-SFCL is proposed to describe its nonlinear characteristic of inductance. Firstly, the structure and working principle of the dc I-SFCL is briefly introduced, and the magnetic equivalent circuit is established according to the magnetic field distribution. Then, the relationship between dc transient current and the current-limiting inductance of dc I-SFCL is discussed. By analyzing the equivalent magnetic circuit, a mathematical I-SFCL model is proposed in Matlab based on the actual geometric and electrical parameters. Finally, under the same dc test platform, the magnetic flux density, the voltage and the current of dc I-SFCL in Matlab model are compared with that in finite element method (FEM) model. Simulation results verifies the validity and the correctness of the model.

A DC Line Protection Scheme for MMC-Based DC Grids Based on AC/DC Transient Information

With the rapid development of renewable energy, multi-terminal flexible DC grids composed of modular multilevel converters have been widely used in power systems. To ensure the safe and stable operation of a DC grid, this paper proposes a DC line protection scheme for MMC-based DC grids using AC/DC transient information. In the proposed scheme, the difference between the transient voltage root mean square ratios (DTVR) on both sides of the current-limiting inductor of DC lines is used to identify the DC line fault, and the instantaneous zero sequence voltage (IZSV) of the AC side of the converter station is used to discriminate the faulted poles. According to the theoretical analysis result, a fault criterion setting method suitable for faulted pole discrimination is proposed. The proposed scheme is based on local information and tested in a PSCAD/EMTDC model of a four-terminal MMC-based DC grid. The simulation results show that the scheme can fast and accurately identify faults.

A Hybrid DC Circuit Breaker with Fault-Current-Limiting Capability for VSC-HVDC Transmission System

The direct current circuit breakers are considered a promising option to protect the transmission line against commonly appearing line-to-ground fault. However, the challenges of losses in the nonoperational stage, escalation of response against fault current, and large fault current handling capability remain the debatable issues for direct current circuit breakers. This paper introduces a novel topology of the hybrid circuit breaker with fault-current-limiting characteristics, which contains three branches: the main branch, fault-current-limiting branch, and energy absorption branch. The main branch includes a mechanical switch, breaker impedance, and bidirectional power electronics switches. In the fault-current-limiting branch, a fault-current-limiting circuit is introduced which contains n numbers of bidirectional switches and current-limiting inductors, which are connected in series to make the design modular in nature. During the normal working stage, the current flows through the main branch of the breaker. Once a fault in the system is confirmed, the fault current is transferred to the fault-current-limiting branch. At this stage, the intensity of the fault current is reduced significantly using the fault-current-limiting circuit, and finally, the residual current is shifted to the energy absorption branch. The working principle, design considerations, and parametric analysis concerning the design of hybrid circuit breakers are incorporated in this paper. The performance of the proposed breaker is evaluated using a three-terminal voltage-source converter-based high-voltage direct current transmission network; for this purpose, a PSCAD/EMTDC simulation tool is used. The performance of the proposed breaker is also compared with other topologies. The comparative analysis shows that the proposed breaker is a good alternative considering high fault current interruption requirements, response time against fault current, and power losses.

Protection Scheme of Multi-terminal Flexible DC Distribution Network Based on Current-Limiting Inductor Voltage

The rapid development of power electronic devices has promoted the rapid development of multi-terminal flexible DC distribution networks, indicating the direction of DC technology and urban power distribution systems. However, there are several technical problems in multi-terminal flexible DC distribution network that still need to be solved. In relay protection, the main difficulty faced by DC distribution network is the rapid and reliable identification of DC faults. This paper proposes a multi-terminal flexible DC distribution network protection scheme based on current-limiting inductor. First, the system configuration of the multi-terminal flexible DC distribution network is introduced. Then, the DC-side fault characteristic of the flexible DC distribution network are analysed. Based on this, a protection scheme based on current-limiting inductor voltage is proposed. Next, a complete protection scheme is designed. Finally, the proposed protection scheme is verified by real time digital simulator (RTDS). The simulation results show that the scheme is not affected by the fault resistance and fault distance.

Enhanced Fault Current-Limiting Circuit Design for a DC Fault in a Modular Multilevel Converter-Based High-Voltage Direct Current System

The main weakness of the half-bridge modular multilevel converter-based high-voltage direct current (MMC-HVDC) system lies in its immature solution to extremely high current under direct current (DC) line fault. The development of the direct current circuit breaker (DCCB) remains constrained in terms of interruption capacity and operation speed. Therefore, it is essential to limit fault current in the MMC-HVDC system. An enhanced fault current-limiting circuit (EFCLC) is proposed on the basis of fault current study to restrict fault current under DC pole-to-pole fault. Specifically, the EFCLC consists of fault current-limiting inductance L F C L and energy dissipation resistance R F C L in parallel with surge arrestor. L F C L reduces the fault current rising speed, together with arm inductance and smoothing reactor. However, in contrast to arm inductance and smoothing reactor, L F C L will be bypassed via parallel-connected thyristors after blocking converter to prevent the effect on fault interruption speed. R F C L shares the stress on energy absorption device (metal oxide arrester) to facilitate fault interruption. The DCCB requirement in interruption capacity and breaking speed can be satisfied effortlessly through the EFCLC. The working principle and parameter determination of the EFCLC are presented in detail, and its effectiveness is verified by simulation in RT-LAB and MATLAB software platforms.

Transients outrush current analysis and mitigation: A Case study of Afghanistan North East power system

This study evaluates the inconveniences raised by the installation of Shunt Capacitor Banks (SCB) along the North East Power System (NEPS) in Afghanistan. Besides the numerous advantages, a capacitor bank usually has some drawbacks in terms of transient currents which affect the quality of power supply and exceed the withstand capability of associated equipment. In this study, transient outrush current injects by installed SCB into the nearby faulted point at Pule Khumri and Chimtala substations is investigated. Outrush transient is produced by SCB when the breaker is operating to disconnect the faulted circuit. By applying different methods can mitigate outrush transient and protect the system which Current Limiting Inductance (CLI) is preferred in this study. Integrating CLI in series with SCB is the most relevant method which can limit the amplitude, frequency, and the rate of rise of the outrush transient. The use of inductance could otherwise create some excessive voltage which might exceeds the withstand capability of circuit breakers. Hence sensitivity analysis based on Transient Recovery Voltage (TRV) to confirm the robustness of the proposed approach is carried out. The evaluation is accomplished based on the result derived from the Electromagnetic Transients Program (EMTP), ATP package.

Design of a Proportional Resonant Controller with Resonant Harmonic Compensator and Fault Ride Trough Strategies for a Grid-Connected Photovoltaic System

This paper presents the design and analysis of a proportional resonant controller with a resonant harmonic compensator and switch-type fault current limiter, as a fault-ride through strategy for a three-phase, grid-connected photovoltaic (PV) system under normal conditions and asymmetrical faults. The switch-type fault limiter comprised of current-limiting inductors, a bridge rectifier, a snubber capacitor, linear transformers, and energy absorption bypass. Furthermore, a critical and analytical comparison of switch-type fault limiters is carried out, with the conventional crowbar as the fault-ride through strategy, in combination with a conventionally tuned proportional integrator controller. The designed fault-ride through strategies with proportional integrator and proportional resonant controllers with resonant harmonic compensators are tested at the point of common coupling of the photovoltaic system and at a distance of 19 km from the point of common coupling, in order to analyze the impacts of fault parameter with respect to location. A MATLAB/Simulink model of a 100 kW three-phase grid-connected photovoltaic system is used for analysis. The simulation results of the proposed switch-type fault limiter with proportional resonant controller effectively validate the stable, ripple-free, and robust response compared to all other configurations. In addition, it is also verified that the grid faults on the PV system have a significant impact on fault type, and less impact on fault location.