Current Latch Sense Amplifier Research Articles

Cache Memory Design for Single Bit Architecture with Different Sense燗mplifiers

Most modern microprocessors have one or two levels of on-chip caches to make things run faster, but this is not always the case. Most of the time, these caches are made of static random access memory cells. They take up a lot of space on the chip and use a lot of electricity. A lot of the time, low power is more important than several aspects. This is true for phones and tablets. Cache memory design for single bit architecture consists of six transistors static random access memory cell, a circuit of write driver, and sense amplifiers (such as voltage differential sense amplifier, current differential sense amplifier, charge transfer differential sense amplifier, voltage latch sense amplifier, and current latch sense amplifier, all of which are compared on different resistance values in terms of a number of transistors, delay in sensing and consumption of power. The conclusion arises that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34 μW of power which shows that power is reduced up to 83%, 77.75% reduction in the case of the current differential sense amplifier, 39.62% in case of charge transfer differential sense amplifier and 50% in case of voltage latch sense amplifier when compared to existing latch sense amplifier architecture. Furthermore, power reduction techniques are applied over different blocks of cache memory architecture to optimize energy. The single-bit six transistors static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique consumes 8.078 μW of power, i.e., reduce 28% more power that makes single bit six transistor static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique more energy efficient.

Dynamic Read Current Sensing With Amplified Bit-Line Voltage for STT-MRAMs

This brief presents a novel sensing approach for spin-based memories that augments the read sense margin and improves read decision failure without deteriorating read disturb by changing the read current dynamically according to the bit-cell state. The proposed sensing circuit consists of three main sub-circuits: 1) the bit-cell; 2) bit-line amplifier; and 3) a standard current-latch sense amplifier. The bit-line amplifier is a basic amplifier with positive feedback connection to achieve higher sense margin with dynamic read current. As a result, the significant increase in the sense margin eliminates the effect of the sense amplifier offset on read decision failure. Monte Carlo simulations in 45 nm demonstrate that the proposed sensing scheme improves the read bit error rate (BER) by more than one order of magnitude compared to the conventional voltage sensing scheme with a cost of 0.3% array area overhead and 3% energy penalty. Moreover, quantitatively compared with some of the state-of-the-art sensing schemes, the proposed scheme achieves a better area-energy-robustness trade-off.

Design and investigation of variability aware sense amplifier for low power, high speed SRAM

Reducing the input referred offset voltage of a sense amplifier (SA) provides remarkable returns in terms of reliability and energy conservation in static random access memory (SRAMs), which consume dominating portion of total power in modern ICs. High-reliability-applications benefit significantly from a low offset SA which can operate at high speed. However, low offset SAs tend to have significant overheads in terms of area, speed and complexity. In this paper we introduce a high speed SA that employs a self correction scheme to greatly minimize its input referred offset. Minimal calibrating circuitry limits the area and energy overheads. Sensing and failure mechanisms have been described for the first time in terms of resistance states of critical paths in SA, to provide a new and more basic dimension in the analysis of the offset problem. We implemented a CMOS logic- compatible, 4 Kb SRAM macro, in commercial UMC 65nm, using the proposed SA namely, self correcting sense amplifier (SCSA). Performance analysis reveals a 60% reduction in standard deviation of input referred offset in SCSA compared to conventional current latch sense amplifier (CLSA). Compared to another modern low offset alternative, SCSA have a 78% lower sensing delay and 19% lower active power consumption resulting in 82% reduction in the power delay product.

Comparative Analysis of Leakage Reduction Techniques in Voltage Mode and Current Latch Sense Amplifiers in Sram Cell

In present paper, the comparative analysis of different type of low power reduction techniques has been performed by implementing in voltage mode and current latch sense amplifier 6-T SRAM cell. The low power reduction techniques have been realized in 6-T SRAM sense amplifiers using the 90-nm 1-V CMOS technologies. Total power dissipation of current latch sense amplifier is 14 μw which is 41.59 percent less than the voltage mode sense amplifier. It has been found that Sleep transistor technique is very effective to reduce leakage power as well as total power dissipation in voltage mode sense amplifier. However, this technique is not so efficient to reduce total power dissipation in current latch sense amplifier. Furthermore, it has been observed that Dual Sleep method is more effective to reduce total power dissipation in current latch sense amplifier.

A High Performance Current Latch Sense Amplifier with Vertical MOSFET

A High Performance Current Latch Sense Amplifier with Vertical MOSFET

Design and application of CMOS bulk input scheme

This work presents CMOS bulk input differential logic (BIDL) circuits. The bulk input scheme is applied to enable bulk terminals to receive signals. A boost circuit is employed to the bulk terminal of an input device. A multiple-input boost circuit is also developed to improve the flexibility of logic design. A current latch sense amplifier is used to generate a pair of full-swing output signals without dc power dissipation. The devices in the differential logic network are connected in parallel, leading to a low parasitic resistive and capacitive load. The BIDL has better speed and power performance than conventional differential logic circuits. The flexibility of the logic design is greatly improved. The BIDL is applied to a divide-by-128/129 frequency synthesizer using a 0.25-/spl mu/m CMOS process. Measurement results of the test chip indicate that the operating frequency is 2 GHz at a supply voltage of 2.5 V.

A 0.25-μm 3.0-V 1T1C 32-Mb nonvolatile ferroelectric RAM with address transition detector and current forcing latch sense amplifier scheme

Nonvolatile 32-Mb ferroelectric random access memory (FRAM) with-a 0.25-/spl mu/m design rule was developed by using an address transition detector (ATD) control scheme for the application to SRAM and applying a common plate folded bit-line cell scheme with current forcing latch sense amplifier (CFLSA) for increasing sensing margin, and adopting a dual bit-line reference voltage generator (DBRVG) for high noise immunity. Compared to a conventional FRAM device, the total chip size is reduced by 10.87%, which was achieved by using a single section data line (SSDL) and removing large gate-oxide capacitors, which is typically used for reference voltage generator for 1T1C FRAM. Furthermore, the imbalance of reference bit-line capacitance and main bit-line capacitance was resolved by using the CFLSA technique.