Current Digital-to-analog Converter Research Articles

A VCO-Based 2nd-Order Δ2–ΔΣ Modulator for Small-Size High Energy-Efficient Current Sensing Front-End

In this letter, a 2nd-order 2 -Σ modulator consisting of a voltage-controlled-oscillator-based quantizer (VCOQ) and a current digital-to-analog converter (DAC) with a pulse width modulator (PWM) is presented for the precise acquisition of a wide range photocurrent in an area-and energy-efficient form factor. The proposed 2-modulation realized by the 2nd-order infinite impulse response (IIR) filter on the feedback significantly attenuates the magnitude of input signals, enhancing the DR and linearity. Moreover, an additional differentiator followed by the VCOQ features the negative feedback loop in the 2nd-order Σ modulator, improving noise shaping with no additional current DAC noise. In addition, a 1-bit PWM current DAC substituting the multi-bit current DAC is devised to mitigate the noise from the current DAC, realizing the high resolution of 1 pA with 500 Hz bandwidth. The prototype chip fabricated in a 110-nm CMOS occupies 0.0308 mm2 and achieves Walden FoM of 4.15 pJ/conv.

Development of an on-chip configurable DAC module for monolithic active pixel sensor

This paper describes an on-chip configurable Digital to Analog Converter (DAC) module for monolithic active pixel sensor. The DAC module consists of four 10-bit voltage DACs, seven 8-bit current DACs, a bandgap circuit, and a configure interface. The voltage DAC is implemented with an R-2R resistor ladder network, and each LSB corresponds to 3 mV. The current DAC is in the current-steering type with a thermometer code. Each LSB of the current DAC corresponds to 10 nA. The bandgap circuit provides a stable, temperature-independent reference voltage of 1.25 V to the DACs. All the DACs can be accessed and configured with the configure interface. The DAC module covers 3074 µm × 400 µm, and the total power consumption is 46.2 mW. This paper will discuss the design and performance of this DAC module.

Low-Noise Chopper Amplifier Using Lateral PNP Input Stage With Automatic Base Current Cancellation

This brief presents a low-noise chopper amplifier that uses a lateral PNP input stage with automatic base current cancellation in complementary metal–oxide–semiconductor (CMOS) process. A bipolar junction transistor (BJT) input stage can achieve lower noise level than the MOS transistor input stage, but its base current causes low DC input impedance. To enhance the DC input impedance of the BJT input stage, an automatic base current cancellation circuit is implemented using a 10-bit current digital-to-analog converter (DAC) and a successive approximation register (SAR) logic. The output current of the DAC tracks the base current of the BJT input stage using a binary search operation of the SAR logic, and the current DAC provides a cancellation current to the base of the BJT input stage to cancel the input base current. The amplifier is implemented in 0.18- $\mu \text{m}$ CMOS process, and the proposed amplifier occupies an active area of 0.297 mm2. The current consumption of the chopper amplifier is 146 $\mu \text{A}$ with 3.3 V supply voltage. The input referred noise of the chopper amplifier is 5.53 nV $/\surd $ Hz. The input bias current of the proposed amplifier with lateral PNP input stage implementing automatic base current cancellation is 0.391 nA.

A K-Band Variable-Gain Phase Shifter Based on Gilbert-Cell Vector Synthesizer With RC–RL Poly-Phase Filter

A K-band variable-gain phase shifter using a Gilbert-cell vector synthesizer with a current digital-to-analog converter (DAC) and an RC-RL poly-phase filter (PPF) is presented, which is fabricated with a 65-nm RF CMOS process. It controls both gain and phase with low phase and gain variations as well as a low insertion loss. The Gilbert cell synthesizes a vector by summing in-phase (I) and quadrature (Q) phase signals of which the amplitudes are decided by the tail currents of the summing cells, respectively. The tail currents are given by current DACs, which are particularly designed to make the synthesizer have a constant output impedance in all phase and gain states. Because the gain and phase control resolutions depend on those of the current DACs, the size and insertion loss of the variable-gain phase shifter are not dependent on the control resolutions. The total root-mean-square (rms) phase and gain errors are measured to be 0.488° and 0.098 dB for 4096 states of the 7-bit 360° phase and 5-bit 17.8-dB gain controls, respectively, which are calibrated with extra 2-phase and 1-gain control bits. It shows -3.5 dB maximum gain including ON-chip balun losses with 6.6-mW dc power consumption.

Unified Analog PUF and TRNG Based on Current-Steering DAC and VCO

This work presents a unified weak physical unclonable function (PUF) and a true random number generator (TRNG) based on the current-steering digital-to-analog converter (DAC) and ring voltage-controlled oscillator (VCO). Entropy source for the weak PUF is the mismatch between NMOS and PMOS transistors in a cascode current DAC as well as the mismatch between VCO quantizers, while entropy source for the TRNG is thermal noise in the DAC and VCO and clock jitter. Instead of using spatial entropy sources for the PUF, i.e., multiple unit PUF elements, the proposed architecture utilizes temporal entropy source by capturing the output of unit PUF element over multiple cycles, which reduces area significantly. A unified PUF/TRNG prototype is fabricated in 65-nm CMOS and consumes 0.36 pJ/bit at a throughput of 100 Mb/s. The PUF has a measured intra-HD of 0.0906 and inter-HD of 0.4859, while the raw TRNG bitstream has an entropy of 0.9991 and passes all the NIST statistical randomness tests.

A Highly Linear 8-Bit M–2M Digital-to-Analog Converter for Neurostimulators

M-2M current digital-to-analog converter (DAC) is one of the best architectures for the implantable stimulation systems where the available area near the tissue is restricted. However, due to the nonlinear behavior of the employed transistors, the conventional M-2M DAC does not resemble an accurate resistive R-2R ladder. This is due to the fact that the operating point and therefore the drain-source resistance of each transistor depend not only on its location in the ladder, but also on the selected digital input code. Therefore, in this brief, a highly linear M-2M current DAC is proposed that alleviates the effect of the selected digital input code by replacing the employed fixed resistive dump load with an array of resistors controlled by the input code. Moreover, a correction circuit is utilized to improve the nonlinearity effect caused by the location of each transistor in the ladder. The proposed circuit is designed and simulated in a 0.13-μm CMOS technology. Post-layout simulation results show that the proposed M-2M DAC achieves a spurious-free dynamic range (SFDR) of 56.2 dB and signal-to-noise-and-distortion ratio (SNDR) of 46.7 dB at the cost of 25 μW power consumption for the reference current of 20 μA.

Digital Preemphasis in Optical Communication Systems: On the DAC Requirements for Terabit Transmission Applications

Next-generation coherent optical systems are geared to employ high-speed digital-to-analog converters (DAC), allowing for digital preprocessing of the signal and flexible optical transport networks. However, one of the major obstacles in such architectures is the limited resolution (less than 5.5 effective bits) and –3 dB bandwidth of commercial DACs, typically limited to half of the currently commercial baud rates, and even relatively reduced in case of higher baud rate transponders (400 Gb/s and 1 Tb/s). In this paper, we propose a simple digital preemphasis (DPE) algorithm to compensate for DAC-induced signal distortions, and exhaustively investigate the impact of DAC specifications on system performance, both with and without DPE. As an outcome, performance improvements are established across various DAC hardware requirements (effective number of bits and bandwidth) and channel baud rates, for m-state quadrature amplitude modulation (QAM) formats. In particular, we show that lower order modulation formats are least affected by DAC limitations, however, they benefit the most from DPE in extremely challenging hardware conditions. On the contrary, higher order formats are severely limited by DAC distortions, and moderately benefit from DPE across a wide range of DAC specifications. Moreover, effective number of bit requirements are established for m-state QAM, assuming low and high baud rate transmission regimes. Finally, we discuss the application scenarios for the proposed DPE in next-generation terabit transmission systems, and establish maximum transportable baud rates, which are shown to be used toward increasing channel baud rates to reduce terabit subcarrier count or toward increasing forward error correction (FEC) overheads to reduce the pre-FEC bit error rate threshold. Maximum baud rates after DPE are summarized here for polarization multiplexed BPSK, QPSK, 8QAM, and 16QAM, assuming two DACs: Current commercial DACs (5.5 effective bits, 16 GHz bandwidth) 57, 54, 51, and 48 Gbaud, respectively. Next-generation DACs (7 effective bits, 22 GHz bandwidth): 62, 61, 60, and 58 Gbaud, respectively.

The architecture design of a 2mW 18-bit high speed weight voltage type DAC based on dual weight resistance chain

At present, the architecture of a digital-to-analog converter (DAC) in essence is based on the weight current, and the average value of its D/A signal current increases in geometric series according to its digital signal bits increase, which is 2n−1 times of its least weight current. But for a dual weight resistance chain type DAC, by using the weight voltage manner to D/A conversion, the D/A signal current is fixed to chain current Icha; it is only 1/2n−1 order of magnitude of the average signal current value of the weight current type DAC. Its principle is: n pairs dual weight resistances form a resistance chain, which ensures the constancy of the chain current; if digital signals control the total weight resistance from the output point to the zero potential point, that could directly control the total weight voltage of the output point, so that the digital signals directly turn into a sum of the weight voltage signals; thus the following goals are realized: (1) the total current is less than 200 μA; (2) the total power consumption is less than 2 mW; (3) an 18-bit conversion can be realized by adopting a multi-grade structure; (4) the chip area is one order of magnitude smaller than the subsection current-steering type DAC; (5) the error depends only on the error of the unit resistance, so it is smaller than the error of the subsection current-steering type DAC; (6) the conversion time is only one action time of switch on or off, so its speed is not lower than the present DAC.

27.1: An Area‐Effective Source Driver with 12‐Bit Linear DAC for Large‐Size TFT‐LCDs

AbstractAn area‐effective 12‐bit linear digital‐to‐analog converter (DAC) of source driver is proposed for large‐Size TFT‐LCDs. The proposed DAC is composed of resistor‐string DAC for MSB 6‐bit, current DAC for LSB 6‐bit and interpolation amplifiers. To reduce the area of DAC, 6‐bit current DAC is designed using low voltage devices. We designed and fabricated the source driver with the proposed DAC using 0.13 μm process with 2.5 V low voltage devices and 16 V high voltage devices. One channel layout area is 17.5 μm × 600 μm, which is shrunk by 15% compared with that of 8‐bit resistor‐string DAC. The experimental results show that the output voltage deviation is less than 3.5 mV.

A High-Performance Current-Mode Source Driver IC for Mobile Active Matrix Organic Light Emitting Diode Displays

In this paper, we describe two types of 8-bit current-mode driver ICs with a small area and good performance for applications high accuracy current-mode digital-to-analog converters (DACs), and improved channel-to-channel uniformity for active matrix organic light-emitting diode (AMOLED) displays. One uses the proposed current steering DAC (type A), which is an improved architecture of a binary-weighted DAC, and the other uses a DAC that is a combination of a thermometer-decoded of the DAC and a binary-weighted type. The measured results show that the peak integral nonlinearity (INL) is within ±0.5 the least significant bit (LSB), the peak differential nonlinearity (DNL) is within ±0.5 LSB, and the nonuniformity of output current among channels and chips is within ±0.5 LSB. The size of the driver IC is 15,820 ×1,500 µm2 and the total power consumption of the current-mode driver IC is less than 9 mW when the display has full-white pattern with a luminance of 150 cd/m2. The chip area and power consumption with the proposed current DAC are reduced by 26 and 10%, respectively, compared with those of conventional driver ICs with a fully binary-weighted DAC.

Current Programming Method with Voltage-Variation-Sensing and Current-Feedback Operations for Active Matrix Organic Light-Emitting Diodes

In active matrix organic light-emitting diodes (AMOLEDs), there are two driving methods: voltage programming and current programming methods. The voltage programming method has a short programming time, but its uniformity is sensitive to the characteristics of driving thin film transistors (TFTs). On the other hand, the current programming method is insensitive to the characteristics of driving TFTs but has a long programming time. Therefore, we propose a new driving method with voltage-variation-sensing and current-feedback operations to resolving these problems. The proposed driving method is carried out to detect the voltage variations of a current digital-to-analog converter (DAC), and a fast charging/discharging panel using an additional current source. A programming method using an additional current source is a successive approximation method. In successive approximation methods, charging or discharging through the voltage variation of the current DAC is selected. However the voltage variation of the current DAC is small, thus, we proposed a detection circuit using a unit gain operational amplifier. Simulation results show that the current through an organic light-emitting diodes (OLEDs) reaches a values of 17 nA in 20 µs when the data programming time is 52 µs in a 2.2-in. quarter-video graphic array (qVGA) of AMOLEDs. For the remaining 32 µs, the current DAC compensates the current difference.

Measurement and compensation of digital-to-analog converter nonlinearity

A novel method of finding digital-to-analog converters (DACs) input sequences to produce high-fidelity output waveforms is presented. Error produced by a nonideal DAC is represented by its spectral components. Successive power spectrum measurements are used to solve for the unknown amplitude and phase of compensation signals applied to the DAC input. This iterative technique has produced waveforms that have a 35-dB reduction in harmonic distortion. This iterative method of finding error can also be used to develop dynamic models of the error introduced by the DAC based on current and previous DAC input codes. These models can predict and correct errors produced from an arbitrary input sequence. An evaluation of this technique is done using a commercially available 12-bit DAC.