Cu-pillar Bump Research Articles

Isothermal aging and electromigration reliability of Cu pillar bumps interconnections in advanced packages monitored by in-situ dynamic resistance testing

Cu pillar bump (CPB) technology as the representative advanced packaging technology possesses the characteristics of miniaturization and high density, thus playing an important role in the reliability of electronic devices. However, the brittle intermetallic compound (IMC) layer in the joints evidently affects the service performance and reliability of CPB joints. Thus, the influence of IMC layer thickness and microstructure needs to be carefully evaluated. In this study, the reliability of CPB joints with different IMC layer thickness under the condition of isothermal storage and room-temperature electromigration was tested, and the effect of initial IMC thickness of joints on the reliability was revealed. The full-IMC joints have the best isothermal storage reliability while the half-IMC joints perform the worst. Meanwhile, the thin-IMC joints own the best electromigration reliability but the full-IMC joints show the worst because that the initial voids in full-IMC joints accelerate the failure caused by electromigration.

Synthesis and Atomic Transport of CoSn3 NanoIMC by In Situ TEM.

In order to optimize the interfacial properties by adding Co to the bumps of copper pillars and to overcome the strong tendency of Co to oxidize, an intermetallic compound (IMC) "capsule" was developed for the purpose of transporting elements through the intermetallic compound. In this study, we present a comprehensive analysis of the transformation process of CoSn2 nanoparticles into CoSn3 at the nanoscale using in situ heating transmission electron microscopy (TEM). The experimental results reveal that CoSn2 nanoparticle growth occurs through polymerization, whereas CoSn3 nanoparticle formation relies on the reaction between CoSn2 and Sn. During the initial stages of the reaction, Co dissolves and diffuses into Sn, leading to the nucleation and growth of CoSn2 in Sn via Ostwald ripening. As the input energy increases, vacancies in CoSn2 drive a reaction at the Sn/CoSn2 interface, resulting in the generation of CoSn3. In this process, Sn nanoparticles enter the CoSn2 structure through the "Anti Structure Bridge (ASB) mechanism" to fill vacancies. Following the codeposition process, CoSn3 nanoparticles were successfully plated within the Sn layer of the Cu-pillar bumps. Upon reflow heating, the CoSn3 nanoparticles exhibited a preference for precipitating the vacant sites within the Sn layer. This process facilitated the release of Co atoms from CoSn2, enabling their diffusion throughout the entire Sn layer.

Flip-Chip Flux Evolution

Abstract Flip-chip assembly accounts for more than 80% of the advanced packaging technology platform, compared to fan-in, fan-out, embedded die, and through silicon via (TSV). Flip-chip interconnect remains a critical assembly process for large die used in artificial intelligence processors; thin die that warps at elevated temperatures; heterogeneous integration in SiP applications; flip-chip on leadframe; and MicroLED die usage. This paper will first outline trends in evolving flip-chip and direct chip placement (DCP) technology, then will examine the changing nature of the solder bump, the interconnect itself, and the substrate. Many variables of the flip-chip assembly process will be discussed, including standard solder bumps to micro Cu-pillar bumps with different alloys; different pad surface finishes of Cu OSP, NiAu, and solder on pad (SOP); and from regular pads on substrates to bond-on-trace applications. A major focus will be on flip-chip assembly methods, from old C4 conventional reflow processing to thermocompression bonding (TCB), and the latest laser assisted bonding (LAB) technology, with an emphasis on how the usage of different technologies necessitates different assembly materials, especially fluxes. Flip-chip fluxes such as the commonly used water-washable flux, the standard no-clean flux, and the ultra-low residue flux, and how these fluxes react to different processing methods, will be an area of discussion. Finally, the paper will examine the need for increased reliability as the technology inevitably moves into the high-volume, zero-defect arena of automotive electronics.

Improvement of Adhesion by UV Irradiation for the Formation of Cu-Pillar Bumps

Improvement of Adhesion by UV Irradiation for the Formation of Cu-Pillar Bumps

Viscoplasticity Behavior of a Solder Joint on a Drilled Cu Pillar Bump Under Thermal Cycling Using FEA

Although the copper (Cu) pillar bump (CPB) was developed in accordance with recent trends of miniaturized, multifunctional, and high-performance technology, its thermomechanical reliability remains in question. Accordingly, a hole was drilled into a CPB to increase its thermomechanical reliability, and the viscoplasticity behaviors of the two structures were subsequently compared through finite element analysis. In particular, this study applied the Anand model, which addresses both plastic strain and creep strain, as well as a submodeling technique to increase the accuracy of the analysis and decrease the analysis time. In addition, this study confirmed the superiority of the thermomechanical reliability of drilled Cu pillar bump through a hysteresis loop, which showed the equivalent stress versus equivalent inelastic strain of the solder joint interfaces. Moreover, the study compared the inelastic strain energy density values. The results demonstrated that the drilled copper pillar bump does indeed have a smaller inelastic range and a lower inelastic strain energy density.

Thermal fatigue reliability for Cu-Pillar bump interconnection in flip chip on module and underfill effects

Purpose – The purpose of this paper is to assess the thermo-mechanical reliability of a solder bump with different underfills, with the evaluation of different underfill materials. As there is more demand in higher input/output, smaller package size and lower cost, a flip chip mounted at the module level of a board is considered. However, bonding large chips (die) to organic module means a larger differential thermal expansion mismatch between the module and the chip. To reduce the thermal stresses and strains at solder joints, a polymer underfill is added to fill the cavity between the chip and the module. This procedure has typically, at least, resulted in an increase of the thermal fatigue life by a factor of ten, as compared to the non-underfilled case. Yet, this particular case is to deal with a flip chip mounted on both sides of a printed circuit board (PCB) module symmetrically (solder bump interconnection with Cu-Pillar). Note that Cu-Pillar bumping is known to possess good electrical properties and better electromigration performance. The drawback is that the Cu-Pillar bump can introduce high stress due to the higher stiffness of Cu compared to the solder material. Design/methodology/approach – As a reliability assessment, thermal cyclic loading condition was considered in this case. Thermal life prediction was conducted by using finite element analysis (FEA) and modified Darveaux’s model, considering microsize of the solder bump. In addition, thermo-mechanical properties of four different underfill materials were characterized, such as Young’s modulus at various temperatures, coefficient of temperature expansion and glass transition temperature. By implementing these properties into FEA, life prediction was accurately achieved and verified with experimental results. Findings – The modified life prediction method was successfully adopted for the case of Cu-Pillar bump interconnection in flip chip on the module package. Using this method, four different underfill materials were evaluated in terms of material property and affection to the fatigue life. Both predicted life and experimental results are obtained. Originality/value – This study introduces the technique to accurately predict thermal fatigue life for such a small scale of solder interconnection in a newly designed flip chip package. In addition, a guideline of underfill material selection was established by understanding its affection to thermo-mechanical reliability of this particular flip chip package structure.

Effect of intermetallic compound thickness on shear strength of 25 μm diameter Cu-pillars

The chip-to-chip bonding technique using Cu-pillars bump is widely applied in 3D chip stacking technology. The excessive growth of intermetallic compounds (IMC) is expected to increase the propensity to brittle failure. Typically, the thickness of the IMC layer is used to indicate the risk of failure of solder joints. This study investigates the effects of Cu6Sn5 and Cu3Sn compounds on the single-joint shear strength of Cu-pillar bumps 25 μm in diameter joined with Sn–3.5 wt%Ag–0.7 wt%Cu (SAC 357) alloy. The influence of heat treatment on the shear strength of the Cu-pillar structures is studied by applying two types of heat treatment: (i) a standard conveyor furnace process and (ii) isothermal holding at 240 °C for holding times up to 30 min. The change in mechanical strength was then established as a function of total IMC thickness through shear test experiments. Shear strength was measured with different displacement rates of 70, 130 and 500 μm s−1. The shear height, from the tip of the shear tool to Cu pad substrate, varied from 11 μm to 16 μm in 1 μm steps. The variation in shear force values through the interfacial system, from pure Cu-pillar to solder ball, are discussed in relation to the failure shape observations. For low shearing heights (11–12 μm), mainly Cu material is probed and high shear force values are measured. For high shearing heights (15–16 μm), the probed materials are Cu6Sn5 and Sn and low shear force values are measured. For intermediate shearing heights (13–14 μm) the probed materials are Cu3Sn and Cu6Sn5 and the Cu/Cu3Sn interface seems to be as strong as the Cu3Sn/Cu6Sn5 interface, despite the fact that almost all the Kirkendall voids are located in Cu/Cu3Sn interface.

The Fine Pitch Cu-pillar Bump Interconnect Technology Utilizing NCP Resin, Achieving the High Quality and Reliability

The Fine Pitch Cu-pillar Bump Interconnect Technology Utilizing NCP Resin, Achieving the High Quality and Reliability

Electro-migration Behavior in Eutectic Sn-Bi Flip Chip Solder Joints with Cu-Pillar Electrodes

This paper discusses electro-migration behavior of eutectic Sn-Bi solder with Cu-pillar bumps. Two types of under bump metal (UBM) of organic substrate were studied, that is, Cu pad and electroless Ni/Au plated on Cu pad. The current density was 4x104A/cm2 at 125 and 150 degree C. Bi quickly migrated to accumulate on the anode side(Cu-pillar) and Sn migrated to the cathode side (Substrate pad). Both the case of surface finishes, although the resistivity was increased to approximately 80 % during approximately 80 hours, it was stabilized more than 2800 hours and there were no electrically break failure. From the cross-sectional analyses of eutectic Sn- Bi solder joints after the test, it was found that Bi layer and intermetallic compound (IMC) behaved as the barriers of the Cu atom migration into Sn solder.

Electroless Ni Plating to Compensate for Bump Height Variation in Cu–Cu 3-D Packaging

The feasibility of electroless Ni plating to compensate the Cu bump height variation in Cu-Cu 3-D packaging was investigated. After fabricating Cu pillar bump and Cu micro-stud structure on the top and bottom chips, respectively, Cu-Cu thermocompression bonding and then electroless Ni plating were sequentially carried out and evaluated using dies shear force, daisy chain resistance, and microstructure. It is found that thermocompression bonding parameter optimization and Ar plasma surface cleaning increased the Cu-Cu bond strength. The electroless Ni plating can compensate for the bump height variation of 1.9 μm in a chip with filling the gap between the Cu-pillar bump and Cu-micro-stud structure. In addition, the electroless plated Ni reduced the daisy chain resistance with the increase of the contact area. The resistance of bump daisy chains after electroless Ni plating was measured to be about 15% lower than that obtained after Cu-Cu thermocompression bonding.

Optimization of Ag Composition in Cu Pillar Bumps with Sn-xAg Solders

In order to minimize the large plate growth of Ag3Sn intermetallic compounds (IMCs) adversely affecting the mechanical behavior and reducing the reliability of solder joints, the Ag content of less than 3wt% has been suggested in ball grid array (BGA) Sn-Ag solders. The suggestion (< 3wt% Ag in the solders) is invalid in small solder bumps, and moreover there is no available guideline of the Ag content in the small Sn-Ag solders. In this study, the optimum level of Ag content in small Sn-Ag Cu pillar bumps (CPBs) of less than 50um in diameter was investigated to suppress the large plate growth of Ag3Sn. Since the undercooling of Sn-Ag solders increases with a decrease of solder ball size, the Ag3Sn IMCs are more prone to become largely plate-like in small solders. Actually, in small Sn-Ag CPBs, the large plate growth of Ag3Sn was observed on the top surface of solder bumps even though the Ag content was less than 3.0wt%. For suppression of Ag3Sn plates in Sn-Ag CPBs, two ways were suggested; increasing the cooling rate of the reflow profile and reducing the Ag content in the solders. Reducing the Ag content was effective on reducing the large plate growth of Ag3Sn, while a high cooling rate was not effective. Through the thermal analysis and thermodynamic calculations, the optimized Ag content in Sn-Ag CPBs of less than 50um was suggested, and the large plate growth of Ag3Sn was effectively reduced within the suggested Ag content.

Simulation of Effect of Current Stressing on Reliability of Solder Joints with Cu-Pillar Bumps

Simulation of Effect of Current Stressing on Reliability of Solder Joints with Cu-Pillar Bumps