CTAT Voltages Research Articles

A 210 nW NPN-Based Temperature Sensor With an Inaccuracy of ±0.15 °C (3σ) From −15 °C to 85 °C Utilizing Dual-Mode Frontend

This paper describes an NPN-based temperature sensor that achieves a 1-point trimmed inaccuracy of ±0.15 ∘C (3σ) from –15 to 85 ∘C while dissipating only 210 nW. It uses a dual-mode front-end to roughly halve the power consumption of conventional front-ends. First, two NPNs are used to generate a well-defined PTAT bias current, then this current is sampled and applied to the same NPNs to generate well-defined PTAT and CTAT voltages. These voltages are then applied to a low power tracking Σ modulator-based ADC, which employs a digital filter to efficiently generate a multi-bit representation of temperature. A prototype fabricated in a 180-nm BCD process achieves 15 mK resolution in a 50 ms conversion time, which translates into a state-of-the-art resolution FoM of 2.3 pJK2.

A 24.4 ppm/°C Voltage Mode Bandgap Reference With a 1.05V Supply

This brief proposes a sub-1V, voltage mode CMOS bandgap reference circuit. Conventionally, sub-1V references are obtained by converting PTAT and CTAT voltages to currents and summing them in the current domain. Such techniques have multiple operating points and cannot natively support applications that require PTAT currents in addition to a bandgap voltage. This brief presents a voltage mode reference circuit, which adds a PTAT voltage with a scaled version of a CTAT voltage all within the sub-1V domain. Compared to current mode bandgaps, summing in voltage domain enables reduction of one CTAT current mirror stage and a significant reduction in PTAT current mirror ratio resulting in a reduced number of error sources. In addition, this circuit also natively supports applications that require PTAT current. A novel, high-accuracy self-biasing technique has been adopted to minimize the systematic offset induced temperature coefficient. A prototype designed in 45nm TSMC CMOS technology for a nominal voltage of 500mV demonstrates 24.4ppm/°C temperature coefficient from -40°C to 125°C, 0.15% line regulation, and draws 7.2μ\textA from a 1.05V supply.

A New Sub-1 Volt 17ppm/°C Offset-Insensitive Resistorless Switched-capacitor Bandgap Voltage Reference

A new PVT compensated voltage reference is presented by using switched-capacitor (S.C.) technique. In the proposed bandgap voltage reference (BGR), a p–n junction is biased with different currents during two different phases and required PTAT and CTAT voltages generated and held by two capacitors. Using a capacitive voltage divider, the PTAT voltage is weighted such that the sub-1V bandgap voltage is achievable. In order to cancel the effect of op-amp offset and to relax the design of op-amp, the offset voltage of the op-amp is sampled by a capacitor during a specified phase and inversely is added to the final bandgap voltage in next phase. The analysis of the proposed S.C. BGR is supplemented by simulation of a 0.5-V BGR with 28[Formula: see text][Formula: see text][Formula: see text]W power consumption in a standard 0.18[Formula: see text][Formula: see text][Formula: see text]m CMOS technology. Simulation results show that the average temperature coefficient of the S.C. BGR is 17[Formula: see text]ppm/∘C and it is robust against the process variations. Applying an arbitrary 100-mV op-amp offset results in a lower than 1.1[Formula: see text]mV deviation in generated reference voltage. Due to the better matching of MIM capacitors in CMOS process (rather than resistors used in conventional BGR) the proposed S.C. bandgap provides good accuracy without any post trimming. Monte–Carlo analysis shows that [Formula: see text]/[Formula: see text] of the generated reference voltage is as low as 0.7%. The sensitivity of the proposed BGR to supply variation is also less than 1%/V.

A Sub-1 V nanopower subthreshold current and voltage reference using current subtraction technique and cascoded active load

A sub-1 V, subthreshold current and voltage references are presented using Cascaded Current Mirrors (CCM) as temperature compensator and cascoded transistors as active load. The CCM uses current subtraction concept for temperature compensation of supply independent current generated from Current Generator Circuit (CGC) giving rise to reference current which is fed to active load circuit (ALC). The ALC consists of cascoded PTAT and CTAT voltages to generate supply and temperature independent output reference voltage. The proposed references are implemented and simulated in Cadence Virtuoso using 180 nm CMOS technology model for 0.95–1.8 V supply voltage range. The average output reference voltage of 609.7 mV is obtained with the line regulation of 1.99 mV/V. The supply current of 60.7 nA is found at 0.95 V supply along with Temperature Coefficient (TC) of 44.5 ppm/°C for a temperature range of −20 to 108 °C. A high-value PSRR of −42 dB at 100 Hz and −17 dB at 1 MHz is achieved. It has an area of 0.0082 mm2. The obtained average reference current is 6 nA having a slope of 5.5pA/°C.

Design and implementation of micro-power temperature to duty cycle converter using differential temperature sensing

The CMOS based temperature detection circuit has been developed in a standard 180nm CMOS technology. The proposed temperature sensor senses the temperature in terms of the duty cycle in the temperature range of −30°C to +70°C. The circuit is divided into three parts, the sensor core, the subtractor and the pulse width modulator. The sensor core consists of two individual circuits which generates voltages proportional (PTAT) and complementary (CTAT) to the absolute temperature. The mean temperature inaccuracy (°C) of PTAT generator is −0.15°C to +0.35°C. Similarly, CTAT generator has mean temperature accuracy of ±1°C. To increase thermal responsivity, the CTAT voltage is subtracted from the PTAT voltage. The resultant voltage has the thermal responsivity of 6.18mV/°C with the temperature inaccuracy of ±1.3°C. A simple pulse width modulator (PWM) has been used to express the temperature in terms of the duty cycle. The measured temperature inaccuracy in the duty cycle is less than ±1.5°C obtained after performing a single point calibration. The operating voltage of the proposed architecture is 1.80±10% V, with the maximum power consumption of 7.2μW.