Crosspoint Queued Switch Research Articles

Improved analytical model for performance evaluation of crosspoint‐queued switch under uniform traffic

In this study, a crosspoint-queued (CQ) switch that features a buffer size larger than one and employs the work-conserving random scheduling algorithm under uniform Bernoulli i.i.d. traffic is investigated through both theoretical analysis and simulation. The effect of the crosspoint buffer state on switch performance is modelled and quantified. A novel method for calculating the throughput and delay of a CQ switch with a given switch size, input load, and buffer size is proposed. Compared with existing models, the proposed calculation model offers a simpler and more accurate result, and can serve as a theoretical guide in designing high-speed switch fabrics.

Analyzing the impact of buffer capacity on crosspoint-queued switch performance

We use both theoretical analysis and simulations to study the impact of crosspoint-queued (CQ) buffer size on CQ switch throughput and delay performance under different traffic models, input loads, and scheduling algorithms. In this paper, we present the following. 1) We prove the stability of CQ switch using any work-conserving scheduling algorithm. 2) We present an exact closed-form formula for the CQ switch throughput and a nonclosed- form but convergent formula for its delay using static nonwork- conserving random scheduling algorithms with any given buffer size under independent Bernoulli traffic. 3) We show that the above results can serve as a conservative guide on deciding the required buffer size in pure CQ switches using work-conserving algorithms such as the random scheduling, under independent Bernoulli traffic. 4) Furthermore, our simulation results under real-trace traffic show that simple round-robin and random workconserving algorithms can achieve quite good throughput and delay performance with a feasible crosspoint buffer size. Our work reveals the impact of buffer size on the CQ switch performance and provides a theoretical guide on designing the buffer size in pure CQ switch, which is an important step toward building ultra-highspeed switch fabrics.

Efficient Buffering and Scheduling for a Single-Chip Crosspoint-Queued Switch

The single-chip crosspoint-queued (CQ) switch is a compact switching architecture that has all its buffers placed at the crosspoints of input and output lines. Scheduling is also performed inside the switching core and does not rely on latency-limited communications with input or output line-cards. Compared with other legacy switching architectures, the CQ switch has the advantages of high throughput, minimal delay, low scheduling complexity, and no speedup requirement. However, the crosspoint buffers are small and segregated; thus, how to efficiently use the buffers and avoid packet drops remains a major problem that needs to be addressed. In this paper, we consider load balancing, deflection routing, and buffer pooling for efficient buffer sharing in the CQ switch. We also design scheduling algorithms to maintain the correct packet order even while employing multi-path switching and resolve contentions caused by multiplexing. All these techniques require modest hardware modifications and memory speedup in the switching core but can greatly boost the buffer utilizations by up to 10 times and reduce the packet drop rates by one to three orders of magnitude. Extensive simulations and analyses have been done to demonstrate the advantages of the proposed buffering and scheduling techniques. By pushing the on-chip memory to the limit of current ASIC technology, we show that a cell drop rate of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-8</sup> , which is low enough for practical uses, can be achieved under real Internet traffic traces corresponding to a load of 0.9.

A new analytical model for the CQ switch throughput calculation under the bursty traffic

Abstract In this paper we propose a new analytical iterative method for the throughput calculation of the Crosspoint Queued (CQ) switch with a random scheduling algorithm under the bursty traffic model. This method is verified by comparing it with the simulation results, which shows a very good match. To the authors’ knowledge, this is the first analytical method for the throughput calculation of such a switch for the bursty traffic model.

Impact of scheduling algorithms on performance of crosspoint-queued switch

The performance analysis of the 32 × 32 crosspoint-queued switch is presented in this paper. Switches with small buffers in crosspoints have been evaluated in the late 1980s but mostly for uniform traffic. However, due to technological limitations of that time, it was impractical to implement large buffers together with switching fabric. The crosspoint-queued switch architecture has been recently brought back into focus since modern technology enables an easy implementation of large buffers in crosspoints. An advantage of this solution is the absence of control communication between linecards and schedulers. In this paper, the performances of four algorithms (longest queue first, round robin, exhaustive round robin, and frame-based round robin matching) are analyzed and compared. The results obtained for the crosspoint-queued switch are compared with the output queued switch. Throughput, average cell latency and instantaneous packet delay variance are evaluated under uniform and nonuniform traffic patterns. The results will show that the longest queue first algorithm has the highest throughput in many simulated cases but the highest average cell latency and delay variance among observed algorithms. It will also be shown that the choice of the scheduling algorithm does not play a role in the switch performance if the buffers are long enough. This will prove that some form of round-robin-based algorithms become a better choice for implementation due to their simplicity, small hardware requirements, and avoidance of the starvation problem, which is a major drawback of the longest queue first algorithm.

Iterative Throughput Calculation for Crosspoint Queued Switch

In this letter, we propose a novel approximate method for throughput calculation of crossbar switch with buffers only in crosspoints, in the case of uniform traffic. It is an iterative method based on the balance equations that describe crosspoint buffer state. Due to some approximations, we derive very simple formulas suitable for matrix calculation. This method gives results very close to the results obtained by numerous simulations, especially for larger switch and long buffers.

Design of an IPTV Multicast System for Internet Backbone Networks

The design of an IPTV multicast system for the Internet backbone network is presented and explored through extensive simulations. In the proposed system, a resource reservation algorithm such as RSVP, IntServ, or DiffServ is used to reserve resources (i.e., bandwidth and buffer space) in each router in an IP multicast tree. Each router uses an Input-Queued, Output-Queued, or Crosspoint-Queued switch architecture with unity speedup. A recently proposedRecursive Fair Stochastic Matrix Decompositionalgorithm used to compute near-perfect transmission schedules for each IP router. The IPTV traffic is shaped at the sources usingApplication-Specific Token Bucker Traffic Shapers, to limit the burstiness of incoming network traffic. The IPTV traffic is shaped at the destinations usingApplication-Specific Playback Queues, to remove residual network jitter and reconstruct the original bursty IPTV video streams at each destination. All IPTV traffic flows are regenerated at the destinations with essentially zero delay jitter and essentially-perfect QoS. The destination nodes deliver the IPTV streams to the ultimate end users using the same IPTV multicast system over a regional Metropolitan Area Network. It is shown that all IPTV traffic is delivered with essentially-perfect end-to-end QoS, with deterministic bounds on the maximum delay and jitter on each video frame. Detailed simulations of an IPTV distribution system, multicasting several hundred high-definition IPTV video streams over several essentially saturated IP backbone networks are presented.

Quality of service provision in combined input and crosspoint queued switches without output queueing match

Packet switches play one of the most critical roles in supporting quality of service (QoS) in computer communication networks. Although the output queued (OQ) switch architecture can achieve optimal QoS performance, it is not a practical architecture for high-speed switching due to the switching fabric speedup, which requires complex implementation. Combined input and crosspoint queued (CICQ) switches employ the crossbar-based switching fabric structure and apply buffers at both ingress port modules and crosspoints inside the switching fabric. This switch architecture is promising to achieve high performance without complex implementation. Current available approaches for QoS provision in CICQ switches are based on the output queueing match technique. Although such approaches can provide bandwidth and delay guarantees, they still require switching fabric speedup, which may significantly increase the implementation complexity of high-speed CICQ switches. In this paper, we compare the QoS performance that can be achieved in CICQ switches with the QoS performance guaranteed by OQ switches. Based on this comparison, we investigate the possibility of achieving equivalent QoS guarantees in a CICQ switch as in an OQ switch without output queueing match, thus with no switching fabric speedup. Our analysis shows that if sufficient crosspoint buffer space is allocated, a CICQ switch employing a typical scheduling algorithm, such as weighted fairing queueing (WFQ), can provide an identical bandwidth guarantee as the OQ switches without any switching fabric speedup, and can achieve equivalent delay performance as the OQ switch by slightly increasing bandwidth allocation.