Crosspoint Buffers Research Articles

Approaching Work-Conserving Scheduling Algorithm for Mixed Unicast and Multicast in Combined Input and Crosspoint Queued Switch

A novel scheduling algorithm supporting mixed unicast and multicast traffic and featured by the longest virtual queue first (LVQF) was proposed for combined input and crosspoint queued (CICQ) architecture. Considering the differences between unicast and multicast traffic, LVQF takes the virtual queue length as the weight value for unicast and multicast queues. The weight setting of LVQF coordinates the fairness of unicast and multicast scheduling efficiently. Moreover, the design of LVQF is characterized by approaching the inherent work-conserving of the output queued architecture. By balancing the occupancy of crosspoint buffers, LVQF maintains the switch operating in a work-conserving state to the largest extend. By introducing the traffic regulation module in CICQ, an enhanced approaching work-conserving (AWC) algorithm developed from LVQF (AWC-LVQF) is proposed to further approach the work-conserving state. Simulation results demonstrate that LVQF and AWC-LVQF algorithms can significantly improve the average latency performance with respect to the existing popular algorithms for CICQ switch. In particular, the performance improvement enlarges as the ratio of multicast traffic increases.

Improved analytical model for performance evaluation of crosspoint‐queued switch under uniform traffic

In this study, a crosspoint-queued (CQ) switch that features a buffer size larger than one and employs the work-conserving random scheduling algorithm under uniform Bernoulli i.i.d. traffic is investigated through both theoretical analysis and simulation. The effect of the crosspoint buffer state on switch performance is modelled and quantified. A novel method for calculating the throughput and delay of a CQ switch with a given switch size, input load, and buffer size is proposed. Compared with existing models, the proposed calculation model offers a simpler and more accurate result, and can serve as a theoretical guide in designing high-speed switch fabrics.

Achieving 100% Throughput for Integrated Uni- and Multicast Traffic without Speedup

Along with the unbounded speedup and exponential growth of virtual queues requirement aiming for 100% throughput of multicast scheduling as the size of the high-speed switches scale, the issues of low throughput of multicast under non-speedup or fixed crosspoint buffer size is addressed. Inspired by the load balance two-stage Birkhoff-von Neumann architecture that can provide 100% throughput for all kinds of unicast traffic, a novel 3-stage architecture, consisting of the first stage for multicast fan-out splitting, the second stage for load balancing, and the last stage for switching (FSLBS) is proposed. And the dedicated multicast fan-out splitting to unicast (M2U) scheduling algorithm is developed for the first stage, while the scheduling algorithms in the last two stages adopt the periodic permutation matrix. FSLBS can achieve 100% throughput for integrated uni- and multicast traffic without speedup employing the dedicated M2U and periodic permutation matrix scheduling algorithm. The operation is theoretically validated adopting the fluid model.

Analyzing the impact of buffer capacity on crosspoint-queued switch performance

We use both theoretical analysis and simulations to study the impact of crosspoint-queued (CQ) buffer size on CQ switch throughput and delay performance under different traffic models, input loads, and scheduling algorithms. In this paper, we present the following. 1) We prove the stability of CQ switch using any work-conserving scheduling algorithm. 2) We present an exact closed-form formula for the CQ switch throughput and a nonclosed- form but convergent formula for its delay using static nonwork- conserving random scheduling algorithms with any given buffer size under independent Bernoulli traffic. 3) We show that the above results can serve as a conservative guide on deciding the required buffer size in pure CQ switches using work-conserving algorithms such as the random scheduling, under independent Bernoulli traffic. 4) Furthermore, our simulation results under real-trace traffic show that simple round-robin and random workconserving algorithms can achieve quite good throughput and delay performance with a feasible crosspoint buffer size. Our work reveals the impact of buffer size on the CQ switch performance and provides a theoretical guide on designing the buffer size in pure CQ switch, which is an important step toward building ultra-highspeed switch fabrics.

Predictive Unicast and Multicast Scheduling in Onboard Buffered Crossbar Switches

In this letter, a predictive unicast and multicast scheduling (PUMS) scheme is proposed for onboard buffered crossbar switches to cope with time-variant traffic composition. The multicast service ratios required with respect to traffic composition ratio are deduced in theory to guarantee stability and fairness. In the proposed scheme, the multicast service ratios are obtained by a real-time traffic prediction in advance. Accordingly, the bandwidth and crosspoint buffers are adaptively assigned. Simulation results indicate that the proposed PUMS exhibits a promising performance under various traffic scenarios with both fixed and time-variant traffic composition ratios.

Efficient Buffering and Scheduling for a Single-Chip Crosspoint-Queued Switch

The single-chip crosspoint-queued (CQ) switch is a compact switching architecture that has all its buffers placed at the crosspoints of input and output lines. Scheduling is also performed inside the switching core and does not rely on latency-limited communications with input or output line-cards. Compared with other legacy switching architectures, the CQ switch has the advantages of high throughput, minimal delay, low scheduling complexity, and no speedup requirement. However, the crosspoint buffers are small and segregated; thus, how to efficiently use the buffers and avoid packet drops remains a major problem that needs to be addressed. In this paper, we consider load balancing, deflection routing, and buffer pooling for efficient buffer sharing in the CQ switch. We also design scheduling algorithms to maintain the correct packet order even while employing multi-path switching and resolve contentions caused by multiplexing. All these techniques require modest hardware modifications and memory speedup in the switching core but can greatly boost the buffer utilizations by up to 10 times and reduce the packet drop rates by one to three orders of magnitude. Extensive simulations and analyses have been done to demonstrate the advantages of the proposed buffering and scheduling techniques. By pushing the on-chip memory to the limit of current ASIC technology, we show that a cell drop rate of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-8</sup> , which is low enough for practical uses, can be achieved under real Internet traffic traces corresponding to a load of 0.9.

A load-balanced crosspoint-queued switch fabric

The fast growth of Internet has created the need for high-speed switches. Recently, the crosspoint-queue switch has attracted attention because of its scalability and high performance. However, the Cross-point-Queue switch does not perform well under non-uniform traffic. To overcome this limitation, the Load-Balanced Cross-point-Queued switch architecture has been proposed. In this architecture, a load-balance stage is placed ahead of the Cross-point-Queued stage. The load-balance stage transforms the incoming non-uniform traffic into nearly uniform traffic at the input port of the second stage. To avoid out-of-order cells, this stage employs flow-based queues in each crosspoint buffer. Analysis and simulation results reveal that under non-uniform traffic, this new switch architecture achieves a delay performance similar to that of the Output-Queued switch without the need for internal acceleration. In addition, its throughput is much better than that of the pure cross-point-queued switch. Finally, it can achieve the same packet loss rate as the cross-point-queue switch, while using a buffer size that is only 65% of that used by the cross-point-queue switch.

A high‐performance switch architecture based on mesh of trees

SUMMARYWith emergence of various new Internet‐enabled devices, such as tablet PCs or smart phones along with their own applications, the traffic growth rate is getting faster and faster these days and demands more communication bandwidth at even faster rate than before. To accommodate this ever‐increasing network traffic, even faster Internet routers are required. To respond for these needs, we propose a new mesh of trees based switch architecture, called MOTS(N) switch. In addition, we also propose two more variations of MOTS(N) to further improve it. MOTS(N) is inspired by crossbar with crosspoint buffers. It forms a binary tree for each output line, where each gridpoint buffer is a leaf node and each internal node is 2‐in 1‐out merge buffer emulating FIFO queues. Because of this FIFO characteristic of internal buffers, MOTS(N) ensures QoS like FIFO output‐queued switch. The root node of the tree for each output line is the only component connected to the output port where each cell is transmitted to output port without any contention. To limit the number of buffers in MOTS(N) switch, we present one of its improved (practical) variations, IMOTS(N) switch, as well. For IMOTS(N) switch architecture, sizes of the buffers in the fabric are limited by a certain amount. As a downside of IMOTS(N), however, every cell should go through log 2N + 1 number of buffers in the fabric to be transmitted to the designated output line. Therefore, for even further improvement, IMOTS(N) with cut‐through, denoted as IMOTS‐CT(N), is also proposed in this paper. In IMOTS‐CT(N) switch, the cells can cut through one or more empty buffers to be transferred from inputs to outputs with simple 1 or 2 bit signal exchanges between buffers. We analyze the throughput of MOTS(N), IMOTS(N), and IMOTS‐CT(N) switches and show that they can achieve 100% throughput under Bernoulli independent and identically distributed uniform traffic. Our quantitative simulation results validate the theoretical analysis. Copyright © 2012 John Wiley &amp; Sons, Ltd.

Throughput analysis of shared-memory crosspoint buffered packet switches

This study presents a theoretical throughput analysis of two buffered-crossbar switches, called shared-memory crosspoint buffered (SMCB) switches, in which crosspoint buffers are shared by two or more inputs. In one of the switches, the shared-crosspoint buffers are dynamically partitioned and assigned to the sharing inputs, and memory is sped up. In the other switch, inputs are arbitrated to determine which of them accesses the shared-crosspoint buffers, and memory speedup is avoided. SMCB switches have been shown to achieve a throughput comparable to that of a combined input-crosspoint buffered (CICB) switch with dedicated crosspoint buffers to each input but, with less memory than a CICB switch. The two analysed SMCB switches use random selection as the arbitration scheme. The authors modelled the states of the shared-crosspoint buffers of the two switches using a Markov-modulated process and prove that the throughput of the proposed switches approaches 100% under independent and identically distributed uniform traffic. In addition, the authors provide numerical evaluations of the derived formulas to show how the throughput approaches asymptotically to 100%.

Load-Balanced Combined Input-Crosspoint Buffered Packet Switches

Combined input-crosspoint buffered (CICB) switches can achieve high switching performance without speedup. However, the dedicated crosspoint buffers in a CICB switch may not be efficiently used, and throughput degradation may occur. This throughput degradation is especially observable under flows with high data rates and long distances between the line cards and the buffered crossbar. This paper introduces two load-balanced CICB switches: the load-balancing CICB switch with full access (LB-CICB-FA) and the load-balancing CICB switch with single access (LB-CICB-SA). The proposed switches use the crosspoint buffers efficiently and support long distances between the line cards and buffered crossbar with crosspoint buffers smaller than those in a CICB switch by a factor of N, where N is the number of ports. It is proven that the LB-CICB-FA switch with random selection of the configuration of the load-balancing stage, input queues, and crosspoint queues is weakly stable under admissible independent and identical distributed (i.i.d.) traffic. Additional simulation results support the correctness of the theoretical analysis. Furthermore, it is shown that the throughput of the LB-CICB-SA switch with the longest-queue first (LQF) and first-come first-served (FCFS) as input and output arbitrations, respectively, is 100% under admissible i.i.d. traffic. The proposed switches keep cells in sequence and use no speedup. The low implementation complexity of the load-balancing stage is discussed and shown to be small.

QoS가 보장된 멀티캐스트 서버스를 위한 Blocking Avoidance 셀 할당 기법과 Virtual Threshold 기법을 이용한 CICQ 스위치 구조

최근 다양한 멀티미디어 서비스의 등장으로 멀티캐스트를 통한 컨텐츠의 전송이 빠르게 늘어나고 있으며 이를 처리하기 위한 스위치 기술의 중요성이 높아지고 있다. CICQ 스위치 구조는 cross point의 버퍼를 이용하여 HoL blocking 확률을 낮출 수 있으며 스케줄링이 간단하다는 장점이 있지만 트래픽의 부하가 높아짐에 따라 멀티캐스트 트래픽의 처리율이 급격히 떨어질 수 있다는 단점이 있다. 이를 해결하기 몇몇의 멀티캐스트 셀 할당 기법들과 입력 포트와 cross point 사이의 스케줄링 기법들이 제안되었지만 여전히 멀티캐스트 트래픽의 충분한 처리율을 보장하지 못한다. 따라서 본 논문에서는 BA 셀 할당 기법과 VT 기법을 제안하여 멀티캐스트 트래픽의 HoL blocking 확률을 낮추고 cross point 버퍼의 전용 공간을 확보하여 멀티캐스트 트래픽의 처리율을 보장 할 수 있도록 하였다. 또한 시뮬레이션을 통해 제안된 방법을 이용하여 QoS를 향상시킬 수 있음을 확인하였다. Recently the multicast based contents transmission is rapidly increasing due to the various multimedia services and the importance of switching technology to handle it is increasing as a consequence. Though the CICQ architecture has advantages that reduction of HoL blocking probability and simple scheduling using cross point buffer, it has disadvantage that the processing rate of multicast traffic can be significantly degraded corresponds to the traffic load increment. Several schemes have been proposed to solve this problem however they still can't provide enough processing ratio for multicast traffic. Therefore this paper proposes the BA cell assignment scheme and the VT scheme, and the processing rate of multicast traffic can be guaranteed by reducing the HoL blocking probability of multicast traffic and reservation of cross point buffer. Also simulation results verify that using the proposed scheme, the QoS of multicast service can be improved.

Contention-tolerant crossbar packet switches

We propose an innovative agile crossbar switch architecture called contention-tolerant crossbar, denoted by CTC(N). Unlike the conventional crossbar and the crossbar with crosspoint buffers, which require complex hardware resolvers to grant one out of multiple output requests, CTC(N) can tolerate output contentions by a pipelining mechanism, with pipeline stages implemented as buffers in input ports. These buffers are used to decouple the scheduling task into N independent parts in such a way that N schedulers are located in N input ports, and they operate independently and in parallel. Without using arbiters and/or crosspoint buffers that require additional chip area, the CTC(N) switch is more scalable than existing crossbars. We analyze the throughput of CTC(N) switch, and find 63% throughput bottleneck. For achieving 100%, we consider two approaches: using internal speedup and using space multiplexing without internal speedup. We prove that 100% throughput can be achieved with internal speedup 2 or using two layers of CTC(N) fabric mathematically. Our simulation results validate our theoretical analysis. Copyright © 2010 John Wiley & Sons, Ltd.

Impact of scheduling algorithms on performance of crosspoint-queued switch

The performance analysis of the 32 × 32 crosspoint-queued switch is presented in this paper. Switches with small buffers in crosspoints have been evaluated in the late 1980s but mostly for uniform traffic. However, due to technological limitations of that time, it was impractical to implement large buffers together with switching fabric. The crosspoint-queued switch architecture has been recently brought back into focus since modern technology enables an easy implementation of large buffers in crosspoints. An advantage of this solution is the absence of control communication between linecards and schedulers. In this paper, the performances of four algorithms (longest queue first, round robin, exhaustive round robin, and frame-based round robin matching) are analyzed and compared. The results obtained for the crosspoint-queued switch are compared with the output queued switch. Throughput, average cell latency and instantaneous packet delay variance are evaluated under uniform and nonuniform traffic patterns. The results will show that the longest queue first algorithm has the highest throughput in many simulated cases but the highest average cell latency and delay variance among observed algorithms. It will also be shown that the choice of the scheduling algorithm does not play a role in the switch performance if the buffers are long enough. This will prove that some form of round-robin-based algorithms become a better choice for implementation due to their simplicity, small hardware requirements, and avoidance of the starvation problem, which is a major drawback of the longest queue first algorithm.

SQUID: A Practical 100% Throughput Scheduler for Crosspoint Buffered Switches

Crosspoint buffered switches are emerging as the focus of research in high-speed routers. They have simpler scheduling algorithms and achieve better performance than bufferless crossbar switches. Crosspoint buffered switches have a buffer at each crosspoint. A cell is first delivered to a crosspoint buffer, and then transferred to the output port. With a speedup of 2, a crosspoint buffered switch has previously been proved to provide 100% throughput. In this paper, we propose two 100% throughput scheduling algorithms without speedup for crosspoint buffered switches, called SQUISH and SQUID. We prove that both schemes can achieve 100% throughput for any admissible Bernoulli traffic, with the minimum required crosspoint buffer size being as small as a single cell buffer. Both schemes have a low time complexity of O(log N), where N is the switch size. Simulation results show a delay performance comparable to output-queued switches. We also present a novel queuing model that models crosspoint buffered switches under uniform traffic.

Iterative Throughput Calculation for Crosspoint Queued Switch

In this letter, we propose a novel approximate method for throughput calculation of crossbar switch with buffers only in crosspoints, in the case of uniform traffic. It is an iterative method based on the balance equations that describe crosspoint buffer state. Due to some approximations, we derive very simple formulas suitable for matrix calculation. This method gives results very close to the results obtained by numerous simulations, especially for larger switch and long buffers.

Localized Independent Packet Scheduling for Buffered Crossbar Switches

Buffered crossbar switches are a special type of crossbar switches. In such a switch, besides normal input queues and output queues, a small buffer is associated with each crosspoint. Due to the introduction of crosspoint buffers, output and input contention is eliminated, and the scheduling process for buffered crossbar switches is greatly simplified. Moreover, since different input ports and output ports work independently, the switch can easily schedule and transmit variable length packets. Compared with fixed length packet scheduling, variable length packet scheduling has some unique advantages: higher throughput, shorter packet latency, and lower hardware cost. In this paper, we present a fast and practical scheduling scheme for buffered crossbar switches called Localized Independent Packet Scheduling (LIPS). With LIPS, an input port or output port makes scheduling decisions solely based on the state information of its local crosspoint buffers, i.e., the crosspoint buffers where the input port sends packets to or the output port retrieves packets from. The localization feature makes LIPS suitable for a distributed implementation and thus highly scalable. Since no comparison operation is required in LIPS, scheduling arbiters can be efficiently implemented using priority encoders, which can make arbitration decisions quickly in hardware. Another advantage of LIPS is that each crosspoint needs only L (the maximum packet length) buffer space, which minimizes the hardware cost of the switches. We theoretically analyze the performance of LIPS and, in particular, prove that LIPS achieves 100 percent throughput for any admissible traffic with speedup of two. We also discuss in detail the implementation architecture of LIPS and analyze the packet transmission timing in different scenarios. Finally, simulations are conducted to verify the analytical results and measure the performance of LIPS.

Trends in highly scalable crossbar-based packet switch architecture

A combined input and crosspoint queued (CICQ) switch is receiving significant attention to be the next generation high speed packet switch for its scalability; however, a multi-cabinet implementation of a combined input and crosspoint queued (CICQ) switch unavoidably introduces a large round-trip time (RTT) latency between the line cards and switch fabric, resulting a large crosspoint (CP) buffer requirement. In this paper, virtual crosspoint queues (VCQs) that significantly reduces the CP buffer requirement of the CICQ switch is investigated. The VCQs unit resides inside the switch fabric, is dynamically shared among virtual output queues (VOQ) from the same source port, and is operated at the line rate, making the implementation practical. A threshold-based exhaustive round-robin (T-ERR) arbitration is employed to reduce buffer hogging at VCQ. The T-ERR at VCQ and CP arbiters serves packets residing in a longer queue more frequently than packet residing in a shorter queue. Consequently, the T-ERR, drastically increases the throughput of the CICQ switch with small CP buffers. A multi-cabinet implementation of CICQ switch do not support multicasting traffic well since a combination of small CP buffer in the switch fabric and a large RTT latency between the line cards and switch fabric results in non-work conservation of the intra-switch link. Deployment of multicast FIFO buffer between the input buffer and CP buffer shows a promise. With its ability to achieve high throughput independent of RTT and switch port size, the integration of the VCQ architecture and T-ERR scheduler to the CICQ switch is ideal for supporting ever-increasing Internet traffic that requires higher data rate, larger switch size, and efficient multicasting.

Design and performance of speculative flow control for high-radix datacenter interconnect switches

High-radix switches are desirable building blocks for large computer interconnection networks, because they are more suitable to convert chip I/O bandwidth into low latency and low cost than low-radix switches [J. Kim, W.J. Dally, B. Towles, A.K. Gupta, Microarchitecture of a high-radix router, in: Proc. ISCA 2005, Madison, WI, 2005]. Unfortunately, most existing switch architectures do not scale well to a large number of ports, for example, the complexity of the buffered crossbar architecture scales quadratically with the number of ports. Compounded with support for long round-trip times and many virtual channels, the overall buffer requirements limit the feasibility of such switches to modest port counts. Compromising on the buffer sizing leads to a drastic increase in latency and reduction in throughput, as long as traditional credit flow control is employed at the link level. We propose a novel link-level flow control protocol that enables high-performance scalable switches that are based on the increasingly popular buffered crossbar architecture, to scale to higher port counts without sacrificing performance. By combining credited and speculative transmission, this scheme achieves reliable delivery, low latency, and high throughput, even with crosspoint buffers that are significantly smaller than the round-trip time. The proposed scheme substantially reduces message latency and improves throughput of partially buffered crossbar switches loaded with synthetic uniform and non-uniform bursty traffic. Moreover, simulations replaying traces of several typical MPI applications demonstrate communication speedup factors of 2 to 10 times.

Output-based shared-memory crosspoint-buffered packet switch for multicast services

The incorporation of broadcast and multimedia-on-demand services are expected to increase multicast traffic in packet networks, and therefore in switches and routers. Combined input-crosspoint buffered (CICB) switches can provide high performance under uniform multicast traffic, however, at the expense of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> crosspoint buffers. In this letter, we propose an output-based shared-memory crosspoint-buffered (O-SMCB) packet switch where the crosspoint buffers are shared by two outputs and use no speedup. The proposed switch provides high performance under admissible uniform and nonuniform multicast traffic models while using 50% of the memory used in CICB switches. Furthermore, the O-SMCB switch provides higher throughput than an SMCB switch with buffers shared by inputs, or I-SMCB.

Efficient Variable Length Block Switching Mechanism

Most popular and widely used packet switch architecture is the crossbar. Its attractive characteristics are simplicity, non-blocking and support for simultaneous multiple packet transmission across the switch. The special version of crossbar switch is Combined Input Crossbar Queue (CICQ) switch. It overcomes the limitations of un-buffered crossbar by employing buffers at each crosspoint in addition to buffering at each input port. Adoption of Crosspoint Buffer (CB) simplifies the scheduling complexity and adapts the distributed nature of scheduling. As a result, matching operation is not needed. Moreover, it supports variable length packets transmission without segmentation. Native switching of variable length packet transmission results in unfairness. To overcome this unfairness, Fixed Length Block Transfer mechanism has been proposed. It has the following drawbacks: (a) Fragmented packets are reassembled at the Crosspoint Buffer (CB). Hence, minimum buffer requirement at each crosspoint is twice the maximum size of the block. When number of ports are more, existence of such a switch is infeasible, due to the restricted memory available in switch core. (b) Reassembly circuit at each crosspoint adds the cost of the switch. (c) Packet is eligible to transfer from CB to output only when the entire packet arrives at the CB, which increases the latency of the fragmented packet in the switch. To overcome these drawbacks, this paper presents Variable Length Block Transfer mechanism. It does not require internal speedup, segmentation and reassembly circuits. Using simulation it is shown that proposed mechanism is superior to Fixed Length Block Transfer mechanism in terms of delay and throughput.