Cross-coupled Voltage-controlled Oscillator Research Articles

Design and Optimization of an Ultra-Low-Power Cross-Coupled LC VCO with a DFF Frequency Divider for 2.4 GHz RF Receivers Using 65 nm CMOS Technology

This article presents the design and optimization of a tunable quadrature differential LC CMOS voltage-controlled oscillator (VCO) with a D flip-flop (DFF) frequency divider. The VCO is designed for the low-power and low-phase-noise applications of 2.4 GHz IoT/BLE receivers and wireless sensor devices. The proposed design comprises the proper stacking of an LC VCO and a DFF frequency divider and is simulated using a TSMC 65 nm CMOS technology, and it has a tuning range of 4.4 to 5.7 GHz. The voltage headroom is preserved using a high-impedance on-chip passive inductor at the tail for filtering and enabling true differential operation. The VCO and frequency divider consume as low as 2.02 mW altogether, with the VCO section consuming only 0.47 mW. The active area of the chip including the pads is only 0.47 mm2. The designed VCO achieved a much better phase noise of −118.36 dBc/Hz at a 1 MHz offset frequency with 1.2 V supply voltages. The design produced a much better FoM of −196.44 dBc/Hz compared to other related research.

An integrated spiral DGS and an open stub meander-line resonator in the 0.13-µm BiCMOS technology for a 18-GHz band oscillator

In this paper, an 18 GHz voltage-controlled oscillator (VCO) with improved phase noise (PN) and smaller size is proposed. The filter consists of an open stub resonator and an integrated spiral Defective Ground Structure (DGS) resonator. The proposed oscillator is designed in the 0.13-µm SiGe BiCMOS technology. The differential cross-coupled VCO uses a bandpass filter. In this work, the conventional large-size coil is replaced by a resonator based on our proposed open stub resonator and defected ground structure (DGS) where the filter is equivalent to the large coil and the associated capacitors. The use of the filter results in a great reduction of VCO size, low losses, and low power consumption, hence an enhancement in the quality factor. The integrated spiral DGS is etched on the third metal layer (M3) below an open stub meander line onthe top metal layer (TM2) of the 0.13-µm top metal two (TM2) BiCMOS technology. The proposed VCO has a small die area of 0.089 mm2 and has FoMA of 188.8 dB and a power consumption is 13.38 mw. The simulated carrier frequency and phase noise are 18-GHz and −123.59 dBc/Hz (−103.7 dBc/Hz) at 10-MHz (1 MHz) offset frequency, respectively, which results in a figure of merit of 177.37 dB.

Layout of MOS Varactor with Improved Quality Factor for Cross-Coupled Differential Voltage-Controlled Oscillator Applications

In this study, we designed an MOS varactor for application in the differential voltage-controlled oscillator (VCO). To improve the quality factor of the MOS varactor, we proposed a symmetric layout technique of the MOS varactor with reduced parasitic components. Compared with the typical MOS varactor layout, the metal line for the interconnection of the MOS varactors that is inevitable in the typical MOS varactors for the cross-coupled VCO was minimized to reduce the parasitic resistance. In addition, with the reduced interconnection metal line, the overall size of the proposed MOS varactor was also reduced compared with the typical one. To verify the feasibility of the proposed MOS varactor structure, the typical and proposed MOS varactors were designed using a 180 nm RFCMOS process. Compared to the typical MOS varactor, the measured quality factor of the proposed MOS varactor was improved by approximately 32% at the operating frequency of 5.0 GHz. Additionally, we successfully verified that the parasitic capacitance induced by the lossy silicon substrate was reduced in the proposed MOS varactor structure.

Ku-Band Low Phase Noise VCO Using High-Quality Factor Transformer in 0.18-μm CMOS Technology

This work introduces a low phase-noise (PN) wideband voltage-controlled-oscillator (VCO) by proposing five ports transformer in 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology. The proposed VCO uses five ports transformer and operates in the low band when all the pMOS–nMOS cross-coupled VCO components are activated, whereas this VCO operates in the high band using only part of the transformer, and an nMOS cross-coupled core. The transformer is designed using the top metal layer (M6) and the first inductor is meander line U-shaped center tap inductor, while the second inductor consists of two shunted octagonal loops to increase the quality ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q}$ </tex-math></inline-formula> -) factor compared with using a single-loop inductor. The wideband switched transformer VCO achieves a measured frequency tuning range (FTR) of 16.4–17.1 GHz with a PN of −113.3 dBc/Hz at 1-MHz offset, and from 17 to 17.9 GHz with a PN of −110.3 dBc/Hz at 1-MHz offset in the low and high bands, respectively. The achieved figure-of-merit (FoM) is −189 and −186.4 dBc/Hz in the low and high bands, respectively.

A 78.8-84 GHz Phase Locked Loop Synthesizer for a W-Band Frequency-Hopping FMCW Radar Transceiver in 65 nm CMOS.

A W-band integer-N phase-locked loop (PLL) for a frequency hopping frequency modulation continuous wave (FMCW) radar is implemented in 65-nm CMOS technology. The cross-coupled voltage-controlled oscillator (VCO) was designed based on a systematic analysis of the VCO combined with its push-pull buffer to achieve high efficiency and high output power. To provide a frequency hopping functionality without any overhead in the implementation, the center frequency of the VCO is steeply controlled by the gate voltage of the buffer, which effectively modifies the susceptance of the VCO load. A stand-alone VCO with the proposed architecture is fabricated, and it achieves an output power of 13.5 dBm, a peak power efficiency of 9.6%, and a tuning range of 3.5%. The phase noise performance of the VCO is −92.6 dBc/Hz at 1-MHz and −106.1 dBc/Hz at 10 MHz offset. Consisting of a third-order loop filter and a divider chain with a total modulus of 48, the locking range of the implemented PLL with the cross-coupled VCO is recorded from 78.84 GHz to 84 GHz, and its phase noise is −85.2 dBc/Hz at 1-MHz offset.

Design of optimal high-frequency CMOS VCOs for automotive application

In this paper, a design methodology of Voltage-Controlled Oscillator (VCO) for long-range automotive RAdio Detection And Ranging (RADAR) is proposed and simulation analysis is carried out over Virtuoso SpectreRF software on Cadence tool. The frequency ranges of the mm-wave CMOS current-starved ring and LC VCOs for 45-nm CMOS technology are 24 and 76 GHz, respectively. The ring VCO at 25 GHz oscillation frequency demonstrates 2.06% tuning range, phase noise −71.61 dBc/Hz at 1-MHz offset, 3.43 mW power dissipation and layout area of $$20\times 20 \,\upmu {\mathrm{m}}^2$$ whereas cross-coupled LC VCO achieves an oscillation frequency of 76.25 GHz for frequency tuning range of 0.65%, a phase noise of −92.44 dBc/Hz at 1-MHz offset, 8.59 mW power dissipation and $$320\times 320 \,\upmu {\mathrm{m}}^2$$ layout area. The proposed design of efficient VCOs shows an excellent performance for long-range automotive RADAR.

Design of a Voltage-Controlled Oscillator for Ka-Band Applications

ABSTRACTA varactor-less cross-coupled voltage-controlled oscillator based on triple frequency is presented in this paper, which is optimized for a low phase noise and low power at the high frequency. The VCO consists a voltage to current, a triple frequency, and a mixer with band-pass filter. The varactor-less VCO adjusts the frequency with the current and voltage of transconductance cell. A network RF–CF–RF is applied to filter out the noise of current source at 2. The proposed circuit was simulated in a 0.18 µm CMOS RF technology with a 1.5 V supply voltage. The designed VCO demonstrates an oscillation frequency range from 11.59 to 13.96 GHz with the triple frequency from 35.8 to 40.3 GHz. The simulated VCO presents a phase noise of −110.1 dBc/Hz at 1 MHz offset from a 40.3 GHz carrier frequency. The total figure of merit (FOMT) is −193.113 and −190.83 dBc/Hz with a DC power of 11.32 and 19.56 mW for VCO and total structure, respectively. The layout of the VCO occupies an area of 695.10 µm 627.80 µm.

A Noise Circulating Oscillator

This paper presents a noise circulating cross-coupled voltage-controlled oscillator (VCO) topology with a transformer-based tank. The introduced noise circulating active core greatly suppresses the effective noise power from the active devices while offering the same amount of negative resistance compared to conventional cross-coupled VCO topologies. The mechanism of noise circulation is investigated with theoretical analysis and further verified by simulation. Due to the broadband nature of the noise circulating technique, the resulting VCO phase noise in both 1/ $f^{2}$ and 1/ $f^{3}$ regions is greatly improved over a wide frequency tuning range. A prototype VCO at 2.35 GHz is implemented in a standard 130-nm bulk CMOS process with 0.36-mm2 core area. It draws 2.15 mA from a 1.2-V supply. The measured figure-of-merit (FoM) is 193.1/195.0/195.6 dBc/Hz at 100k/1M/10MHz offsets with a 1/ $f^{3}$ phase noise corner of only 50 kHz. The VCO design consistently achieves >192.8 dBc/Hz FoM at 100k/1M/10MHz offsets and $f^{3}$ phase noise corner over its entire 18.6% frequency tuning range (2.05 − 2.47 GHz). It also exhibits low supply frequency pushing of −25 and −13 MHz/V at the highest and lowest frequencies, respectively.

A low phase noise gm-boosted DTMOS VCO design in 180 nm CMOS technology

This paper presents the design of a low phase noise voltage controlled oscillator (VCO), which offers higher transconductance (gm) by the use of parallel MOSFETs. Here, two NMOS transistors are connected in parallel with the cross-coupled NMOS transistors of a conventional cross-coupled VCO. So, the total negative conductance offered to the circuit to cancel out the parasitic resistance of the LC-tank is increased. This negative conductance is achieved without dealing with larger transistor size or any other passive elements. Hence, power dissipation and silicon area are reduced. Further, dynamic threshold MOSFET (DTMOS) with a capacitive division technique is implemented to increase the voltage swing, leading to a further decrease in phase noise. The proposed VCO is designed and simulated in UMC 180 nm technology. It achieves a tuning range of 1.58–1.60 GHz about 200 MHz, with 6.09 mW power consumption at 1.1 V supply voltage. The phase noise is obtained −40.6 dBc/Hz at 1 kHz and −120.44 dBc/Hz at 1 MHz respectively. So, it should be used in transceiver and PLL blocks for low voltage and low phase noise applications.

Wide-Locking Range Divide-by-4 Injection-Locked Frequency Divider Using Linear Mixer Approach

A novel divide-by-4 injection-locked frequency divider (ILFD) is proposed and was implemented in the TSMC $0.18~\mu \text{m}$ 1P6M CMOS process. Conventional harmonic mixer divide-by-4 ILFD has limited locking range, and this letter shows a wide locking range divide-by-4 ILFD designed with linear mixer technique. At the drain–source bias of 1 V and at the incident power of 0 dBm, the locking range is 3.9 GHz (36.28%) from 8.8 to 12.7 GHz at the power consumption of 3.61 mW. The free-running oscillation frequency is 2.6 GHz. The proposed ILFD is based on a cross-coupled voltage-controlled oscillator.

High-Performance Low-Cost Dual 15 GHz/30 GHz CMOS LC Voltage-Controlled Oscillator

A CMOS LC voltage-controlled oscillator (VCO) capable of covering both the Ku and Ka bands is presented. The Ku-band frequency source is generated from a low-noise cross-coupled LC VCO. A PMOS push-push frequency doubler, together with the inductor of the low-band LC VCO, is adopted to boost the low Ku-band toward high Ka-band. This proposed VCO is implemented in a standard 0.18 $\mu\text{m}$ CMOS with 1.35 V supply voltage. The dual-band VCO consumes a small active area of 0.49 mm $\times$ 0.2 mm and low DC power of 3 mW at both bands. At 1 MHz (10 MHz) offset, the measured output phase noises are −109.30 dBc/Hz (−130.54 dBc/Hz) at 15.126 GHz and −102.33 dBc/Hz (−124.10 dBc/Hz) at 30.251 GHz.

Wide-Locking Range Divide-by-3 Injection-Locked Frequency Divider Through Enhanced 2nd Harmonic

Conventional harmonic mixer divide-by-3 ILFD has limited locking range. This letter shows a wide locking range ÷3 ILFD designed with the enhanced 2nd harmonic technique. The proposed ILFD is based on a cross-coupled voltage-controlled oscillator (VCO) and was implemented in the TSMC $0.18 \mu \!\!\text{m}$ 1P6M CMOS process. At the drain-source bias $V_\mathrm{DD}$ of 0.8 V and at the incident power of 0 dBm, the locking range is 4 GHz (50%), from the incident frequency 6 GHz to 10 GHz. The core power consumption is 7.72 mW and the die area is $0.939\times 0.885 \text{mm}^{2}$ .

A coupled-inductor dual-mode switched voltage-controlled oscillator using GaN-on-Si HEMT technology

ABSTRACTA coupled-inductors dual-mode switch cross-coupled pair voltage-controlled oscillator (VCO) was presented, adopting GaN-on-Si high-electron-mobility transistor technology. The coupled inductors create two resonant frequencies that cover a wide frequency range. The two continuous bands were achieved by using coupled inductors, and the fine-tuning is controlled by varactors. The low and high bands of the VCO were 2.77–3.11 GHz and 3–3.28 GHz, in the Vc range between 10 and 17 V, respectively, which corresponds to a 16.7% (510 MHz) tuning range. The lowest phase noise was −123 dBc/Hz at an offset frequency of 1 MHz, and the highest output power was 17.7 dBm using a 7.5-V power supply.

Low-Power Injection-Locked Zero-IF Self-Oscillating Mixer for High Gbit/s Data-Rate Battery-Free Active Tag at Millimeter-Wave Frequencies in 65-nm CMOS

In this paper, a low-power zero-IF self-oscillating mixer (SOM) for a new generation of high data-rate battery-free, yet active $\mu{\hbox{RFID}}$ tag (a fully integrated RF identification tag on a single CMOS die with no external components, nor packaging) operating at millimeter-wave frequencies is proposed and demonstrated. It exploits, on one hand, the intrinsic mixing properties of an LC cross-coupled voltage-controlled oscillator, and on the other hand, the injection-locking properties in oscillators. By injection locking the SOM’s natural oscillation frequency to the reader’s carrier frequency (a frequency that bears information of the tag: reader-to-tag communication), it enables a direct-conversion to the baseband with no external local oscillator (LO) source (self-mixing), nor RF frequency conversion into IF frequency, therefore significantly reducing its power consumption. Up-link communication (tag-to-reader communication) is performed by up-converting the tag’s data using the same SOM. Furthermore, the in-phase injected energy stabilizes the self-generated LO and enhances the SOM phase noise, resulting into a low-phase noise baseband signal. Using a standard 65-nm CMOS process, a 40-GHz zero-IF SOM was designed, fabricated, and tested. Experimental results exhibit a conversion loss of about 30 dB under $-{\hbox{38-dBm}}$ injected RF power with a power consumption of only 280 $\mu {\hbox{W}}$ during reader-to-tag communication, and 580 $\mu {\hbox{W}}$ during tag-to-reader communication.

Divide-by-4 capacitive cross-coupled injection-locked frequency dividers

Wide locking range is an important parameter for injection-locked frequency divider (ILFD) to cope with the supply voltage variation. This paper proposes a wide locking range divide-by-4 ILFD implemented in the TSMC 0.18 μm 1P6 M CMOS process. The ILFD uses a capacitive cross-coupled voltage-controlled oscillator as the core. The dc gate bias of cross-coupled FETs is smaller than dc drain bias to optimize the power and locking range. Dual-resonance LC resonator is also used to enhance the locking range. At the drain-source bias of 1.2 V, and at the incident power of 0 dBm the measured locking range of divide-by-4 ILFD is 3.3 GHz, from the incident frequency 7.5---10.8 GHz, the percentage is 36.06%. The core power consumption is 11.83 mW. The die area is 0.883 ? 0.851 mm2.

Dual C- and S-Band CMOS VCO Using the Shunt Varactor Switch

This paper proposes a high-performance CMOS voltage-controlled oscillator (VCO) with two subfrequency bands. The VCO consists of two cross-coupled VCOs coupled by a pair of mode-switched inductors. Two pairs of shunt varactors are used to switch high- and low-frequency bands. With the varactors as the mode switches, the odd mode VCO operates at the high frequency (C-band) and the even mode VCO operates at the low frequency (S-band). The proposed VCO has been implemented with the TSMC 0.18- $\mu $ m 1P6M CMOS technology and it can generate differential signals in the frequency range of 5.21–6.66 GHz (IEEE 802.11a) and 3.26–3.84 GHz (IEEE 802.16a) and it also has high output voltage swings at both low- and high-frequency bands. The die area of the dual-band VCO is 0.976 mm $\times 1.092$ mm. At the supply voltage of 0.75 V, the high(low)-band figure of merit is −190.5(−190.4) dBc/Hz.

Wide-locking range LC-tank divide-by-4 injection-locked frequency divider using transformer feedback

A wide locking range, injection locked frequency divider (ILFD) circuit topology is explored. The modulus-four ILFD utilizes a cross-coupled voltage-controlled oscillator in conjunction with transformer feedback, parallel-tuned resonator, and two-segment, series mixers at the injection point. The transformer feedback and two-segment mixing circuit topology achieves a locking range of 2.7 GHz (14.1 to 16.8 GHz) at an injection point bias of 0.9 Vdc and 0 dBm injection power. Spectral measurements at the ILFD output demonstrate proper phase-lock operation and expected phase noise reduction using a high quality signal source at the ILFD input. The ILFD is implemented in the TSMC 0.18 μm 1P6M CMOS process, utilizes a die area of 0.839 × 0.566 mm2 and consumes 16.56 mW. © 2015 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:557–562, 2015.

Injection-locked frequency divider using single-injected dual-injection MOSFETs

A wide locking range and operation range push–push divide-by-4 injection-locked frequency divider (ILFD) is proposed in the paper and was implemented in the TSMC 0.18μm BiCMOS process. The divide-by-4 ILFD uses a cross-coupled voltage-controlled oscillator (VCO) with a parallel-tuned LC resonator for easy startup oscillation and single-ended injected dual-injection transistors. The common drain node of dual injection transistors is AC-tied to the output of a frequency doubler. At the drain-source bias of 0.8V, and at the incident power of 0dBm the operation range of the divide-by-4 is 3.23GHz, from the incident frequency 15.85 to 19.08GHz, the percentage is 18.49%. The locking range of the divide-by-4 is 1.4GHz, from the incident frequency from 17.08GHz to 19.08GHz, the percentage is 11.06%. The core power consumption is 6.53mW. The die area is 0.83×0.597mm2.

Design of Ku‐band transformer‐based cross‐coupled complementary LC‐VCO

A transformer-based cross-coupled complementary LC voltage-controlled oscillator (VCO) is investigated which is capable of operating at the Ku-band frequency range with low power consumption. The VCO simultaneously achieves low phase noise and low power consumption. The VCO demonstrates a measured tuning range of 12.1–13.1 GHz and a phase noise of −116.4 dBc/Hz at 1 MHz at a centre frequency of 12.4 GHz. The VCO consumes 0.96 mW from a 0.45 V supply voltage with a figure of merit of 198.4. It is implemented in a standard 0.13 µm CMOS process with an area of 0.23 mm2.

Indirect Back-Gate Coupling Quadrature LC-VCO

This letter presents a new quadrature voltage-controlled oscillator (QVCO), which consists of two p-core cross-coupled voltage-controlled oscillators (VCOs) using indirect back-gate coupling. In conventional direct-back coupling the resonator's voltage swing, tuning range, and quality factor are respectively limited by the forward-conducting back-gate junction cut-in voltage, diffusion capacitance and small dynamic resistance. To generate quadrature phase signals with strong coupling strength and large output swing, the proposed design uses pMOSFETs as buffers between the back-gate diode and LC tank to eliminate the drawback in existing back gate coupling QVCOs. The proposed CMOS QVCO has been implemented with the TSMC 0.18 μm SiGe 3P6M technology. At the supply voltage of 0.8 V, the total power consumption is 4.4 mW. The free-running frequency of the QVCO is tuneable from 5.96 GHz to 6.60 GHz as the tuning voltage is varied from 0.0 V to 0.8 V. The measured phase noise at 1 MHz frequency offset is -120.5 dBc/Hz at the oscillation frequency of 6.59 GHz and the figure of merit (FOM) of the proposed QVCO is -190.4 dBc/Hz.