Critical Timing Paths Research Articles

Design of Area Efficient Network-On-Chip Router: A Comprehensive Review

The number of uses for cutting-edge technologies has led to a further growth in a single chip's computational capacity. In this case, several applications want to build on a single chip for computing resources. As a result, connecting the IP cores becomes yet another difficult chore. The many-core System-On-Chips (SoCs) are being replaced by Network-On-Chip (NoC) as an on-chip connectivity option. As a result, the Network on Chip was created as a cutting-edge framework for those networks inside the System on Chip. Modern multiprocessor architectures would benefit more from a NoC architecture as its communication backbone. The most important components of any network structure are its topologies, routing algorithms, and router architectures. NoCs use the routers on each node to route traffic. Circuit complexity, high critical path latency, resource usage, timing, and power efficiency are the primary shortcomings of conventional NoC router architecture. It has been difficult to build a high-performance, low-latency NoC with little area overhead. This paper surveys previous methods and strategies for NoC router topologies and study of general router architecture and its components. Analysis is carried out to understand and work for a low latency, low power consumption, and high performance NoC router design that can be employed with a wide range of FPGA families. In the current work, we are structuring a modified four port router with the goals of low area and high performance operation.

Low-latency equal optical path difference sampling for multi-field VLWIR interference signals

The spaceborne Fourier Transform Spectrometer has been utilized for vertical atmospheric soundings with a HgCdTe infrared focal plane arrays (FPAs) detector. However, the VLWIR FPA Fourier spectrometer system faces the difficulty of poor sensitivity due to the major contribution of the system sampling error. In this work, low-latency data acquisition of multi-field VLWIR interference signals based on VLWIR FPA Fourier spectrometer system is realized with an optimized field programmable gate array (FPGA) timing driver scheme and layout algorithm. This scheme can effectively reduce routing delay and constrain critical timing paths, and thus leads to a significant decrease in the deviation of equal optical path difference sampling time from 10.27μs to 0.10μs. Interferograms and spectrograms are efficiently obtained. Furthermore, the average value of noise equivalent spectral radiance (NESR) in VLWIR FPA Fourier spectrometer system, is reduced by 1.75% by timing optimization. In particular, the decay of the NESR can be as high as 15% for some of the pixels. These results illustrate that the proposed scheme will acquire hyperspectral data accurately with VLWIR FPA and meet the needs of rapid soundings development of the Geostationary Interferometric Infrared Sounder (GIIRS) availing a rapid prediction of the appearance of an extreme weather event.

A dynamic voltage scaling circuit design based on critical path replica and time warning techniques

Critical path replica (CPR) is a widely used technique in synchronous digital circuit design. However, the existing CPR technique cannot accurately reflect the timing of the circuit due to local process variations (LPV). An improved CPR technique based on load capacitance matching (LCM) is proposed in this paper, which can track critical path delay across wide voltage range. The impact of LPV is simulated under wide voltage range, and a configurable delay line is designed to eliminate the effect of LPV. Furthermore, a low overhead mixed-threshold transition detector (TD) circuit is also proposed to monitor timing violations of the replica path, which generate an ‘error’ signal used to dynamically regulate the chip’s operating voltage. The proposed techniques are implemented on a CORDIC chip using the 55-nm CMOS process. Simulation results show that in the near-threshold voltage (NTV) region, the supply voltage can be reduced from 0.8 to 0.6 V, enabling a maximum of 42.6% power saving at the TT corner, 25°C with lesser than 1% area overhead as compared to the baseline design.

Multi-Objective Production and Scheduling Optimization of Offshore Wind Turbine Steel Pipe Piles Based on Improved Hesitant Fuzzy Method

This paper investigates the multi-objective optimization problem in the production of offshore wind turbine steel pipe piles (OWTSPP). Considering the particularity of the steel pipe pile production process, it is divided into a flexible flow shop scheduling (FFSS) stage and an open parallel shop scheduling (OPSS) stage, respectively. Mathematical models are established for each stage, and the critical path and production time information are obtained using a disjunctive graph model. Due to the inability of existing empirical scheduling methods to balance production goals, an improved Pythagorean hesitant fuzzy method (IPHFM) is proposed to solve the multi-objective optimization problem in steel pipe pile production. Specifically, the maximum completion time, machine total load, and total completion time are taken as optimization objectives. The improved Lagrange multiplier method with penalty terms is used to handle the constraints and objective functions, and a Lagrange objective function is generated. Then, the Lagrange objective function matrix is obtained by normalization and same-scale processing, and an algorithm is designed to obtain the Pareto front solution set. Finally, this paper compares the optimal scheduling plans under the empirical scheduling method and the improved method. The results show that the improved method can significantly improve production efficiency in both small-scale and large-scale production, with improvements of 15.7% and 22.16%, respectively.

Static Timing Analysis of Different SRAM Controllers

Timing-critical path analysis is one of the most significant terms for the VLSI designer. For the formal verification of any kinds of digital chip, static timing analysis (STA) plays a vital role to check the potentiality and viability of the design procedures. This indicates the timing status between setup and holding times required with respect to the active edge of the clock. STA can also be used to identify time sensitive paths, simulate path delays, and assess Register transfer level (RTL) dependability. Four types of Static Random Access Memory (SRAM) controllers in this paper are used to handle with the complexities of digital circuit timing analysis at the logic level. Different STA parameters such as slack, clock skew, data latency, and multiple clock frequencies are investigated here in their node-to-node path analysis for diverse SRAM controllers. Using phase lock loop (ALTPLL), single clock and dual clock are used to get the response of these controllers. For four SRAM controllers, the timing analysis shows that no data violation exists for single and dual clock with 50 MHz and 100 MHz frequencies. Result also shows that the slack for 100MHz is greater than that of 50MHz. Moreover, the clock skew value in our proposed design is lower than in the other three controllers because number of paths, number of states are reduced, and the slack value is higher than in 1st and 2nd controllers. In timing path analysis, slack time determines that the design is working at the desired frequency. Although 100MHz is faster than 50MHz, our proposed SRAM controller meets the timing requirements for 100MHz including the reduction of node to node data delay. Due to this reason, the proposed controller performs well compared to others in terms slack and clock skew.

BULANIK CPM İLE DOĞRUSAL PROGRAMLAMA: İNŞAAT ENDÜSTRİSİNDE BİR VAKA ÇALIŞMASI

İnşaat sektöründe karmaşık projelerin planlanması ve kontrolü için Kritik Yol Metodunun (KYM), yaygın olarak kullanılan yararlı bir araç olduğu kanıtlanmıştır. Ancak, faaliyetlerin süresi net sayılarla temsil edildiğinden, kritik yol analizinde faaliyet sürelerini kesin olarak tahmin etmek zorlaşır. Buna ek olarak, vakaların çoğu, görev sürelerinin sübjektif olarak hesaplanmasını gerektirir ve bu da faaliyetlerin süresi hakkında belirsizliğe neden olur. Bu makale, bulanık kümelere dayalı bir yaklaşım önererek bu sorunları ele almaktadır. Bu çalışmanın amacı, bir inşaat projesinin kritik yolunu ve tamamlanma süresini hesaplamak için bulanık sayıların nasıl kullanılacağını göstermektir. Çalışma kapsamında proje faaliyetlerine üçgen bulanık süreler verilerek iki ayrı çözüm algoritması oluşturulmuştur. Örnek bir inşaat projesinin kritik yolu ve proje süresi ilk çözüm algoritmasında proje faaliyetlerine üçgen bulanık süreler atanarak ve doğrusal programlama modeli kullanılarak hesaplanırken, ikinci çözüm algoritmasında bulanık proje süresi ve kritik yol Alfa kesme yöntemi (α -Kesme Yöntemi) kullanılarak hesaplanmış ve daha sonra Centroid yöntemi (Alanların Merkezi Yöntemi) kullanılarak netleştirilmiştir. Bu proje için kritik yol ve tamamlanma süresi önceden bilindiğinden, iki çözüm algoritması karşılaştırılmıştır. Kritik yol yöntemi yerine Bulanık kritik yol yönteminin kullanılmasının bu çalışmanın önemini vurgulayacağı umulmaktadır.

Hardware functional obfuscation with ferroelectric active interconnects

Existing circuit camouflaging techniques to prevent reverse engineering increase circuit-complexity with significant area, energy, and delay penalty. In this paper, we propose an efficient hardware encryption technique with minimal complexity and overheads based on ferroelectric field-effect transistor (FeFET) active interconnects. By utilizing the threshold voltage programmability of the FeFETs, run-time reconfigurable inverter-buffer logic, utilizing two FeFETs and an inverter, is enabled. Judicious placement of the proposed logic makes it act as a hardware encryption key and enable encoding and decoding of the functional output without affecting the critical path timing delay. Additionally, a peripheral programming scheme for reconfigurable logic by reusing the existing scan chain logic is proposed, obviating the need for specialized programming logic and circuitry for keybit distribution. Our analysis shows an average encryption probability of 97.43% with an increase of 2.24%/ 3.67% delay for the most critical path/ sum of 100 critical paths delay for ISCAS85 benchmarks.

Project Time Deployment: a new lean tool for losses analysis in Engineer-to-Order production environments

This paper presents a novel lean tool called Project Time Deployment (PTD) whose objectives are to classify, analyse, and eliminate losses in order to reduce production lead time in Engineer-to-Order (ETO) environments. By combining two already known approaches, i.e. the Manufacturing Critical-path Time and the Manufacturing Cost Deployment, PTD identifies the critical losses affecting the project, focusing on the business processes where causal losses occur, and providing opportunities for greater efficiency and effectiveness by reducing or even eliminating them. In ETO projects, the lead time and respecting deadlines are of paramount importance and they are often threatened by several different losses that are difficult to compare. Companies thus need a tool to identify the losses and the tasks where they occur, quantifying them in terms of a single dimension: the time. PTD was designed using a methodology based on four steps: analysis of current solutions, concept design and prototype, proof of concept and validation, and definition of future researches. It was also validated in an industrial implementation concerning an Engineering, Procurement & Construction company operating in the steel industry, and led to an approximate 24% reduction in lead time.

Quick-Scan – Towards a Strategy for Responsive and Resilient Value Chains

To remain competitive in today’s increasingly dynamic and complex environments, manufacturing enterprises must build resilience to respond to changes quickly. As such, lean production has provided firms with an alternative to "fat and lazy" mass production. In addition, Quick Response Manufacturing has been presented as a credible supplement to lean production, specifically in High Mix, Low Volume environments. Drawing on practical insights from two case studies, we present a Quick-Scan method as an initial step towards creating resilient and responsive value chain strategies. The approach combines manufacturing critical-path time mapping from Quick Response Manufacturing with Gemba-based discovery and learning from Lean - to find, face, and frame real problems, and thereafter form solutions together with managers and front-line personnel. The method has been adopted in both cases as a means of revitalizing operations with the intention of enabling more effective delivery of customer-specific products.

SYSTEM DYNAMICS MODEL FOR FLOW TIME AND LOT SIZES OPTIMIZATION ACCORDING TO QUICK RESPONSE MANUFACTURING (QRM) STRATEGY

The aim of this paper is to propose a simulation model based on system dynamics and the elements that compose Quick Response Manufacturing (QRM) strategy. The developed model is a very useful decision-making tool, since it facilitates the obtaining of process flow times and lot sizes in manufacturing environments that focus their competitive strategy on markets that demand a high variability and product customization. Through simulating four different scenarios, the effects of variability and machine resources utilization are evaluated. The results show that a minimal change in machine resources utilization causes a high impact on process flow times and consequently, on another critical QRM variable such as Manufacturing Critical-Path Time (MCT). Keywords: Simulation, System dynamics, Quick response manufacturing, Flow time; Operations management

Analysis and proposal of reduction of lead time in the process of cutting, loading and transportation in a sugar cane factory: a study case

Abstract This article parts from the importance of sugarcane based energy to the Brazilian economy and, consequently, the important role of the process that involves cutting/loading/transportation (CLT) of cane in the supplies and production cost of sugar, alcohol and its derivates. For this purpose, a study case was carried in a sugarcane factory from São Paulo state, aiming to build a proposal that could reduce the lead time in the CLT process through the analysis of the Manufacturing Critical-Path Time (MCT) of the studied industry. With the data collected in the field visits, the MCT of one tone of sugarcane during its logistic process was done. This tool revealed a long waiting time of the cane waiting to be milled in the patio of the factory. Through the theory of dynamic of the systems it was concluded that this time was high due to the variability of the field as a consequence of an inefficient use of the harvester and the logistic system of dynamic allocation of the transportation resources ahead in the harvest. To make the harvester more efficient, a reduction of 40% of the laying time “awaiting transshipment” was proposed, which would result in a save of R$ 1.172.784,00/year. For this reduction five proposals were identified to be implemented in parallel: integration of the systems of the board computer and the traffic control system; integration of the board computers of the harvester and the transports; implementation of truck filling volume sensors; focus in the management of basis leaders; and, implementation of a multitask worker.

OWARU: Free Space-Aware Timing-Driven Incremental Placement With Critical Path Smoothing

This paper presents an incremental timing-driven placement tool, named OWARU. It optimizes timing critical paths through a free space-aware path smoothing: the gates on such paths are relocated to free spaces around the smoothed paths, while incremental static timing analysis is involved to accurately assess timing changes due to the relocation. OWARU is extended to accommodate gate sizing and layer assignment to demonstrate the effectiveness of unified physical synthesis optimizations and incremental placement. The goal is to show that OWARU is an ideal platform for timing closure at later stages of a physical design flow. OWARU is applied on a set of test circuits from 14-nm high-performance commercial microprocessors, which originally failed in timing closure. On average, the worst slack is improved by 63.6%, which corresponds to 5.0% of the clock period; total negative slack is improved by 69.1%.

Implementing Quick Response Manufacturing to Improve Delivery Performance in an ETO Company

As the pressure is increasing to compete with others to get customer orders in the global market, companies are struggling to build up competitive advantages that are hard to imitate. The trend shows more and more customers demand faster product delivery in the last decade. The Quick Response Manufacturing (QRM) approach provides significant benefits to engineer-to-order (ETO) companies through its focus on lead time reduction. A precision parts manufacturer was selected as case study to what extent QRM is a suitable solution to improve the delivery performance. This paper describes the implementation of the QRM concepts and illustrates how they were deciphered into practices that streamline the process across the organization. The study measures the effectiveness of the QRM framework through its ability to achieve better performance through concurrently reducing manufacturing critical-path time, lowering capacity utilization level and increasing throughput.

Definindo uma estratégia make to availability para uma empresa make to stock de linha branca

Neste artigo é abordada a metodologia da manufatura responsiva (Quick Response Manufacturing – QRM) que tem como objetivo reduzir o lead time das operações, aqui, o objeto de estudo será uma empresa de linha branca. A utilização do gráfico Manufacturing Critical-path Time (MCT) permitiu identificar que o estoque de produtos acabados seria a etapa foco de redução de lead time, com este fim, é apresentada uma proposta de adoção de estratégia de produção para disponibilidade (Make to availability – MTA) em substituição a atual estratégia de produzir para estoque (Make to Stock – MTS). O objetivo é reduzir o lead time de produção e, consequentemente, diminuir os custos desses produtos em estoque resultando em redução de aproximadamente 50% no MCT atual.

Fast identification of true critical paths in sequential circuits

The recent advancements in the implementation technologies have brought to the front a wide spectrum of new defect types and reliability phenomena. The conventional design techniques do not cope with the integration capacity and stringent requirements of today's nanometer technology nodes. Timing-critical paths analysis is one of such tasks. It has applications in gate-level reliability analysis, e.g., Bias Temperature Instability (BTI) induced aging, but also several others. In this paper, we propose a fast simulation based technique for explicit identification of true timing-critical paths in both combinational and sequential circuits to enable reliability mitigation approaches, like selecting the paths for delay monitor insertion, resizing delay critical gates or applying rejuvenation stimuli. The high scalability of the method is achieved by using a novel fast method for finding activated paths for many test patterns in parallel, a novel algorithm to determine only a small subset of critical paths, and a novel method for identifying the true critical paths among this subset, using branch and bound strategy. The paper demonstrates efficient application of the proposed technique to gate-level NBTI-critical paths identification. The experimental results prove feasibility and scalability of the technique.

A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging

Temporal unreliability due to aging, such as Negative-Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) effects etc., in the CMOS circuits may not appear just after the chip production, instead it becomes apparent when it is used under certain workload and environmental conditions over time. Identifying aged paths that may become critical to circuit performance, is a real challenge for many researchers and reliability engineers. In this work, firstly we identify a set of parameters that impact the circuit performance under aging and use them in the proposed algorithm which is substantially faster than commercially available SPICE simulator with an approx 94% accuracy in estimating path delays. Secondly, we explore the possibility of using the proposed methodology, instead of using time expensive SPICE and pessimistic static timing analysis (STA), to identify a set of speed-limiting paths under aging. Experimental results demonstrate the effectiveness of the proposed algorithm and the associated methodology in comparison to SPICE simulated results.

Logic Design Partitioning for Stacked Power Domains

Energy and battery lifetime constraints are critical challenges to IC designs. Stacked power-domain implementation, which connects voltage domains in series, can effectively improve power delivery efficiency and thus improve battery lifetime. However, such an approach requires balanced currents between different domains across multiple operating scenarios. Furthermore, level shifter insertion, along with placement constraints imposed by power domain regions, can incur significant power and area penalties. To the best of our knowledge, no existing work performs subblock-level partitioning optimization for stacked-domain designs. In this paper, we present an optimization framework for stacked-domain designs. Based on an initial placement solution, we apply a flow-based partitioning that is aware of multiple operating scenarios, cell placement, and timing-critical paths to partition cells into two power domains with balanced cross-domain current and minimized number of inserted level shifters. We further propose heuristics to define regions for each power domain so as to minimize placement perturbation, as well as a dynamic programming-based method to minimize the area cost of power domain generation. In an updated floor plan, we perform matching-based optimization to insert level shifters with minimized wirelength penalty. Overall, our method achieves an excellent current balance across stacked domains with less than 10% discrepancy, which results in up to more than $2\times$ battery lifetime improvements.

Análise do lead time nos processos logísticos de uma rede varejista de flores

O mercado de flores no Brasil necessita de reestruturação para conseguir oferecer produtos sensíveis com maior qualidade para o consumidor. Essa reestruturação permitirá que as flores cheguem ao consumidor mais rapidamente e com mais tempo de durabilidade. O objetivo deste estudo foi analisar o lead time dos processos logísticos de uma rede varejista de flores com sede na cidade de Campinas/SP, utilizando a ferramenta MCT - Manufacturing Critical-path Time, da abordagem QRM – Quick Response Manufacturing. Algumas ferramentas auxiliaram a pesquisa, como Fluxograma, Mapa de Fluxo de Valor, Diagrama de Ishikawa e Brainstorming. Os dados coletados relacionados aos tempos de processamento das operações levantam características dos processos logísticos envolvidos na distribuição da matéria-prima, desde a sua aquisição até a entrega em cada filial. Ao fim da pesquisa foi possível propor mudanças nos locais de compras das flores e no modo de distribuição para as lojas, simulando a redução no lead time de aproximadamente 80%.

Regression Modelling for Prediction of Construction Cost and Duration

Construction investments are sensitive to time and cost overruns. Delay and cost escalation are considered two threats to project success. The project objective is to develop a model to predict project cost and duration based on historical data of similar projects. Statistical regression models are developed using real data of building projects. The methodology is adopted in 3 steps: a) Data collection b) Statistical analysis using Statistical Package for Social Sciences (SPSS) software c) Interpretation of results. The real data of cost and duration of 51 building projects have been collected. In statistics, regression analysis is a statistical process for estimating the relationships among variables. It includes many techniques for modelling and analyzing several variables, when the focus is on the relationship between a dependent variable and one or more independent variables. The analysis is done using SPSS developed by IBM Corporation. The Regression models have been developed using the data collected from Noel Builders, Kakkanad, Ernakulam to predict the project cost and duration. The developed models are validated using split sample approach. The model outputs can be used by project managers in the planning phase to validate the scheduled critical path time and project budget.

Hybrid-POLCA in Job Shop Manufacturing

With increasing competition and customers’ demand, manufacturers are faced with the challenge of improving throughput and on-time deliveries. This issues is further complicated for job shop manufacturing due to variabilities in demands, process flow and process time. This paper proposes a hybrid material flow control mechanism that combines a dispatching rule with the POLCA system in job shop environment. Data are collected from a case company and discrete event simulation is used to evaluate the Work In Process (WIP), throughput (TP), average Manufacturing Critical path Time (MCT) per job and On-Time Delivery (OTD) for three different flow controls. The performance of each model is evaluated and statistically validated. In this study, the hybrid POLCA performs the best for all performance measures.