Critical Dimension Accuracy Research Articles

Thin-absorber extreme-ultraviolet lithography mask with light-shield border for full-field scanner: flatness and image placement change through mask process

When a thinner absorber mask is practically applied to the extreme ultraviolet lithography for ultra large scale integration chip production, it is inevitable to introduce an extreme ultraviolet (EUV) light shield area to suppress leakage of the EUV light from adjacent exposure shots. We believe that a light-shield border of the multilayer etching type is a promising structure in terms of mask process flexibility for higher mask critical dimension accuracy. We evaluate the etching impact of the absorber and multilayer on the mask flatness and image placement change through the mask process of a thin absorber mask with a light-shield border of the multilayer etching type structure. We clarify the relation between mask flatness and mask image placement shift.

Global Critical Dimension Correction: II

In LSI production, various factors contribute to critical dimension (CD) errors. Factors that gradually affect CD over a several mm–cm area are referred to as global CD errors. In this paper, a method of correcting global CD errors (GCD correction) that appear in processes following an electron-beam mask-writing process is discussed. Examples of GCD errors are the loading effects in wafer and mask processes, and the flare in lithography processes. In this paper, we propose a new method of calculating the optimum dimension to correct GCD errors. The correction method is based on a pattern modulation method; i.e., modification of the sizes of figures in an LSI pattern depending on their position. A feature of our method is the use of two newly introduced factors, a “figure edge contribution” and a “corner adjustment term”, in addition to conventional pattern density. As an example, the correction accuracy of our method is evaluated for mask fabrication by numerical calculation. It is shown that our method can suppress the GCD correction error to less than 0.01 nm when the maximum GCD error depending on the pattern density is 20 nm. Our method will provide the CD accuracy required in the future. The relation between global CD correction and proximity effect correction is also discussed in the case that an electron-beam writing system is used to control figure sizes.

CD and IP accuracy in electron beam character projection technology

CD and IP accuracy in electron beam (EB) character projection (CP) was examined. We measured around 1 nm as critical dimension (CD) 3 sigma of CP line patterns without major and minor deflection. In the case of VSB, the values exceed 2 nm. This gap is based on the difference in the beam formation method of CP and VSB. Root of the difference of these two squares of 3 sigma are from 1.69 to 2.53 nm and it is caused by variation of relative position between beam and CP mask aperture in using VSB. We measured 1.64 nm as CD 3 sigma of CP line patterns with major deflection within 1520 × 680 μm and minor deflection within 80 × 80 μm and analyzed the data into local factor: 1.38 nm, major deflection factor: 0.72 nm and minor deflection factor: 0.51 nm. It seemed that CP technology for CD accuracy had sufficient potential to 45 nm half-pitch system. Then we also measured image placement (IP) accuracy of CP (position, gain and rotation of CP as to changing deflection distance for CP selection, area of CP aperture and major and minor deflection distance). The variation in the position to CP selection was observed and is considered to be due to electric or mechanical vibration of system. For our future 45 nm half-pitch system, we plan to raise the performance of each unit and to lower this variation. The dependence to change of the parameter of the system was also observed: (A) change of the rotation to CP selection deflection distance, (B) change of gain and rotation to CP area and (C) change of gain and rotation to major and minor deflection distance. We could compensate by using biased mask for (A) and (B). We are going to cope with (C) by narrowing major deflection distance.

Improving critical dimension accuracy and throughput by subfield scheduling in electron beam mask writing

Resist heating in high-voltage, high-throughput electron beam (e-beam) mask write is a significant source of critical dimension (CD) distortion. Excessive heating on the reticle determines changes in resist sensitivity, which in turn cause significant CD variation. CD distortions on the reticle are replicated onto the wafer with increased magnitude as determined by the mask error enhancement factor (MEEF). As designs enter the sub-90nm regime, CD variation has a significant impact on performance, performance variation, and product yield. Previous methods for reducing CD distortion include usage of lower e-beam current density, increased delays between electron flashes, and multipass writing. However, all of these methods lower mask writing throughput, which is increasingly becoming a limiting factor in semiconductor industry productivity. In this paper, we propose a novel method for minimizing CD distortion and maximizing mask writing throughput. By scheduling the writing of subfields, we perform simultaneous optimization of mask writing order and e-beam current density. We perform subfield scheduling by evaluating resist temperature of subfield orderings using a fast analytical temperature model. Simulation experiments show that the new subfield scheduling method can reduce the maximum resist temperature up to 12°C over existing sequential writing methods with unchanged mask writing throughput. Alternatively, improved subfield scheduling can enable the use of higher beam current densities, leading to increased writing throughput without compromising CD control.

Complementary exposure of 70 nm SoC devices in electron projection lithography

We demonstrate complementary exposure of 70 nm system-on-a-chip (SoC) devices in electron projection lithography using Nikon’s EB stepper, NSR-EB1A, and a high-performance Si stencil mask (4×) fabricated by HOYA. A gate level of the SoC device pattern data called Anaheim was processed for mask fabrication using a 10 PC-clustered hierarchical data processing system in which complementary splitting was executed by the M-Split developed by Selete and ISS. Data processing times and output data volumes of the complementary split and of proximity effect correction were all drastically reduced by using our hierarchical data processing method. We optimized stitching features to compensate for the critical dimension (CD) changes that can occur with stitching errors caused by complementary exposures. The complementary stitching accuracy obtained was better than 20 nm and the CD accuracy was better than 10 nm for 100 nm line and space patterns because of the use of stitching features.

Fabrication of a continuous diamondlike carbon membrane mask for electron projection lithography

Fabrication of 8 in. high-performance continuous diamondlike carbon (DLC) membrane masks for electron projection lithography is described. The mask substrate materials and structures were optimized by evaluating the lithographic performance of the mask. The optimum mask consists of a sandwich structure, consisting of a thicker DLC scatter/a CrNx etching stopper/and a thin DLC support membrane on a bulk silicon wafer. The internal stress of each film component can be controlled by adjusting the film deposition conditions. A DLC film can be easily etched by oxygen gas, and the CrNx etching stopper has a high etching durability. Highly accurate pattern properties can be obtained while also meeting performance requirements. The critical dimension accuracy of a DLC scatterer was less than ±5% with a 280-nm-feature size in a 135×43 mm field. The electron aperture transmittance of a 44-nm-thick DLC membrane, measured by energy and angular distribution analysis for membrane, was 13 times as high as the 150-nm-thick SiNx membrane.

High-performance proximity effect correction for sub-70 nm design rule system on chip devices in 100 kV electron projection lithography

The proximity effect correction (PEC) system to achieve the practical processing time and data volume for sub-65 nm design-rule system on chip (SoC) devices is improved. The lump method, which is the technique to process several subfields at a time, is used to reduce the processing time for PEC. The hierarchical data processing for PEC is also proposed to reduce the data volume. A PC cluster system has been used to reduce the processing time for PEC. For an actual 70 nm design-rule SoC device data, the processing time has been reduced from 7.8 h to 10.3 min and the data volume has been reduced from 12.4 to 2.6 GB by using the lump method, the hierarchical data processing, and a ten PC cluster system. And, we have confirmed that the required critical dimension accuracy of ±5% is achieved for the device data in the simulation. We have successfully fabricated a full-size 8 in. Si stencil mask using the data with our PEC system for an actual 70 nm design-rule SoC device.

Development of an electron-beam lithography system for high accuracy masks

A mask electron-beam writer for production lines beyond 100 nm was developed. The system HL-7000M is equipped with cell projection function for high critical dimension accuracy. The newly developed technologies are a cell projection optics, objective lens optics, a low distortion stage, a highly accurate control electronics, and high accuracy proximity effect correction hardware. This article describes the details of the electron optics and its performances.

Recent progress in 1×x-ray mask technology: Feasibility study using ASET-NIST format TaXN x-ray masks with 100 nm rule 4 Gbit dynamic random access memory test patterns

This article discusses recent progress in 1×x-ray mask technology in Japan. Proximity x-ray lithography (PXL) using synchrotron radiation light with a wavelength of 0.7–1.0 nm can in principle provide as high a throughput as optical lithography, because PXL and optical lithography both employ photon beams and masks. A high-performance electron-beam mask writer called the EB-X3, suitable for PXL, has been developed by NTT under the Association of Super-Advanced Electronics Technologies (ASET) program. It has a reproducible image placement (IP) accuracy of less than 15 nm. We used the shaped-beam EB-X3 to fabricate 100 nm rule x-ray masks for the gate and contact/hole (C/H) layers of 4 Gbit dynamic random access memory (DRAM) test patterns. The ASET-NIST (National Institute of Standards and Technology) type masks consist of a 350-nm-thick TaBN absorber, a 3-μm-thick SiC membrane (27-mm square membrane area), a 1-mm-thick Si substrate, and a 6.63-mm-thick Pyrex glass frame. We have achieved an IP accuracy for 1×x-ray masks of less than 15 nm at both the gate and C/H levels. The mask-to-mask overlay accuracy between the gate and C/H masks is less than 20 nm; and after magnification correction, it is less than 10 nm. The critical dimension (CD) variations for 100 nm features measured in a 24-mm-square area are less than 100±6.0 nm at both levels. An overlay accuracy for PXL of better than 30 nm (|mean|+3σ) was obtained by the double-exposure method using the XRA volume-production x-ray stepper (Canon, Inc.) and 18 nm overlay ASET-NIST type x-ray masks (gate to contact). An IP reproducibility of less than 7 nm has been achieved for the EB-X3 itself (best data). The resist CD accuracy on the membrane for 4 Gbit DRAM patterns is better than 7 nm (Δ|mean|+3σ=6.6 nm). These data indicate that PXL has the potential for patterning 50 nm node devices with current tools.

Critical-Dimension Controllability of Chemically Amplified Resists for X-Ray Membrane Mask Fabrication

The key issues in highly precise X-ray mask fabrication are the high-performance electron beam writer and the mask process on a thin membrane. By the combination of 100 kV electron beam system EB-X3 and highly sensitive chemically amplified resist, the high resolution and the excellent critical-dimension (CD) uniformity of 50–100 nm line-and-space and isolated-space features were obtained with no proximity correction. Temperature uniformity of various hot plate bakers during the post-exposure bake process and CD controllability of pattern size with chemically amplified resists were studied and the 3σ variation of pattern size written in a membrane using chemically amplified resists was reduced to less than 10 nm with an optimized hot plate baker. As a result, the e-beam sensitivity and writing time for 4G-bit level ULSI patterns of chemically amplified resist were reduced to less than half of those with conventional ZEP-520 resist, while the resolution capability and CD accuracy of the membrane mask with chemically amplified resist UV6-SL were almost equal to those with ZEP-520.

Critical Dimension Control in Synchrotron Radiation Lithography Using a Negative-Tone Chemical Amplification Resist

Total critical dimension (CD) controllability for 0.14 µ m line-and-space in SR lithography was evaluated for all wafer levels. The evaluation was carried out for the CD accuracy between the wafers, in the wafer and in the exposure field. The influence of the exposure process instability to the CD accuracy was also evaluated. The instability of the post exposure baking (PEB) temperature and the post exposure delay (PED) time affects the CD accuracy, and they were estimated to be less than 5 nm, respectively. The CD accuracy at the same point on the X-ray mask was 5.4 nm in the wafer and 10.5 nm between the wafers. It was found that the CD accuracy between the wafers was degraded by the inaccurate exposure dosage caused by the daily change of the SR beam distribution in the vertical direction. In the exposure field, the CD instability due to SR beam nonuniformity was 4.1 nm and that due to the X-ray mask was 15 nm. Consequently, the total CD controllability is presently estimated to be 19.5 nm for all wafer levels and the improvement of the dose repeatability and X-ray mask CD control is required to achieve the CD accuracy of less than 11 nm.

X-ray mask fabrication technology for 0.1 μm very large scale integrated circuits

X-ray mask fabrication using a subtractive process and a 30 kV acceleration voltage electron beam writer was investigated. The dose margin for delineation of fine resist patterns is increased by reducing the resist thickness. Delineation of 0.1 μm patterns in a 0.1-μm-thick resist has approximately the same dose margin as that of 0.2 μm patterns in a 0.3-μm-thick resist. Width error in SiO2 patterns used as an etching mask is decreased by reducing the thickness and adding SF6 to CF4 etching gas. Tantalum absorbers can be etched very accurately with electron cyclotron resonance ion stream etching by taking microloading effects and undercutting into account. Using the 0.1-μm-thick resist, x-ray masks with 0.1 μm large scale integrated circuit patterns are almost perfectly produced and have a critical dimension accuracy of 13 nm.

Coulomb Interaction Effect in Cell Projection Lithography

In cell projection lithography, critical dimension (CD) control is one of the important issues for device fabrication as well as resolution. Because plural patterns are exposed in one shot under the same dose, the proximity effect correction is more difficult than in the conventional variable-shaped beam (VSB) lithography. We have analyzed the CD deviation in order to obtain high CD accuracy of less than 0.02 µ m (range) which is sufficient for manufacturing 1 G dynamic randam access memory (DRAM). We have found that the Coulomb interaction effect plays an important role in CD deviation. We have proposed a new exposure intensity distribution (EID) function which contains a factor introduced for the first time to compensate the proximity effect and the Coulomb interaction effect simultaneously. The results indicate that the new EID function is very effective to compensate the Coulomb interaction effect and improve the CD deviation from 12% (0.03 µ m) to 6% (0.015 µ m) for 0.25 µ m lines-and-spaces (L/S) patterns.