Credit Flow Control Research Articles

Design and performance of speculative flow control for high-radix datacenter interconnect switches

High-radix switches are desirable building blocks for large computer interconnection networks, because they are more suitable to convert chip I/O bandwidth into low latency and low cost than low-radix switches [J. Kim, W.J. Dally, B. Towles, A.K. Gupta, Microarchitecture of a high-radix router, in: Proc. ISCA 2005, Madison, WI, 2005]. Unfortunately, most existing switch architectures do not scale well to a large number of ports, for example, the complexity of the buffered crossbar architecture scales quadratically with the number of ports. Compounded with support for long round-trip times and many virtual channels, the overall buffer requirements limit the feasibility of such switches to modest port counts. Compromising on the buffer sizing leads to a drastic increase in latency and reduction in throughput, as long as traditional credit flow control is employed at the link level. We propose a novel link-level flow control protocol that enables high-performance scalable switches that are based on the increasingly popular buffered crossbar architecture, to scale to higher port counts without sacrificing performance. By combining credited and speculative transmission, this scheme achieves reliable delivery, low latency, and high throughput, even with crosspoint buffers that are significantly smaller than the round-trip time. The proposed scheme substantially reduces message latency and improves throughput of partially buffered crossbar switches loaded with synthetic uniform and non-uniform bursty traffic. Moreover, simulations replaying traces of several typical MPI applications demonstrate communication speedup factors of 2 to 10 times.

Flow control scheduling

We address a problem associated with credit flow control (FC) schemes for buffered switches, namely, the issue of FC bandwidth and FC optimization, i.e. how many and which credits to return per packet cycle. Using simulations, we show that, under the assumption of bursty traffic with uniform or nonuniform destinations, the number of credits to be returned can be reduced to one, independent of switch size and without loss in performance. Moreover, we introduce the concepts of credit contention and credit scheduling. We analyze five credit-scheduling strategies for a range of system and traffic parameters. Our results demonstrate that with a proper credit scheduler the average packet delay is much lower than with conventional schemes.

A new fast message passing communication system for multiprocessor workstation clusters

In this paper, a fast message passing communication architecture (FMP) is proposed in order to reduce the software overhead of communication, which has been a great impediment to the good performance of workstation clusters. A FMP system is implemented over the SUN Ultra2-Myrinet platform. Measurements show that this implementation has achieved a one-way latency of 11.2us for one-byte packets in network communication, and only 4.9us in local communication. Its bandwidth can reach as high as 338Mb/s for 8KB packets in network communication, and more than 770Mb/s in local message passing. These results tell us that FMP can really exploit the performance of supercomputers and high-speed networks. Local communication is implemented through shared memory within a single host, while the methods to decrease overheads of network communication depend on user-level communication protocol, pipeline transmission, credit flow control and multithreading. Furthermore, the whole system provides the interface for both network and local communication.