CPU-GPU Heterogeneous Architecture Research Articles

FDTD Modeling of Nonlocality in a Nanoantenna Accelerated by a CPU–GPU Heterogeneous Architecture and Subgridding Techniques

FDTD Modeling of Nonlocality in a Nanoantenna Accelerated by a CPU–GPU Heterogeneous Architecture and Subgridding Techniques

A dynamic load balancing algorithm for CFD–DEM simulation with CPU–GPU heterogeneous computing

Computational fluid dynamics combined with discrete element method (CFD–DEM) is widely adopted to study particle–fluid multiphase systems. However, due to the global dynamical evolution and the naturally non-uniform distribution of particles, the computational load in parallel computing varies dynamically in each process, leading to significant load imbalance. Thus, a dynamic load balancing (DLB) algorithm is proposed for parallel CFD–DEM simulations in the CPU–GPU heterogeneous architecture. A type of computing load analyzing grid (AG) is developed which covers the entire simulation region. Then Kalman filtering and linear weighted method is used to solve the weight of fluid grids and particles. The domain decomposition scheme is updated according to the weights of AGs dynamically. This DLB method is tested for gas–solid fluidized beds and periodic gas–solid systems of different scales. Results show that the DLB algorithm can significantly speed up CFD–DEM simulation and the highest performance is 2.28 times faster with DLB.

Parallel String Similarity Join Approach Based on CPU-GPU Heterogeneous Architecture

Parallel String Similarity Join Approach Based on CPU-GPU Heterogeneous Architecture

SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU–GPU heterogeneous architectures

Shared last-level cache (LLC) in on-chip CPU–GPU heterogeneous architectures is critical to the overall system performance, since CPU and GPU applications usually show completely different characteristics on cache accesses. Therefore, when co-running with CPU applications, GPU ones can easily occupy the majority of the LLC, making CPU applications starve severely. This imposes significant challenges to the design and management of the shared LLC in CPU–GPU heterogeneous architectures. To improve the overall system performance, we consider integrating conventional SRAM and a new memory technology (i.e., STT-RAM) to enlarge the shared LLC. Furthermore, we propose comprehensive management policies to reduce the contention between CPU and GPU units. Experimental results show that, compared with the conventional SRAM-only LLC design, our proposal improves the performance of CPU workloads by 17% while not hurting GPU ones and reduces the LLC energy consumption by 30% on average.

SHARP

As the relentless quest for higher throughput and lower energy cost continues in heterogenous multicores, there is a strong demand for energy-efficient and high-performance Network-on-Chip (NoC) architectures. Heterogeneous architectures that can simultaneously utilize both the serialized nature of the CPU as well as the thread level parallelism of the GPU are gaining traction in the industry. A critical issue with heterogeneous architectures is finding an optimal way to utilize the shared resources such as the last level cache and NoC without hindering the performance of either the CPU or the GPU core. Photonic interconnects are a disruptive technology solution that has the potential to increase the bandwidth, reduce latency, and improve energy-efficiency over traditional metallic interconnects. In this article, we propose a CPU-GPU heterogeneous architecture called Shared Heterogeneous Architecture with Reconfigurable Photonic Network-on-Chip (SHARP) that clusters CPU and GPU cores around the same router and dynamically allocates bandwidth between the CPU and GPU cores based on application demands. The SHARP architecture is designed as a Single-Writer Multiple-Reader (SWMR) crossbar with reservation-assist to connect CPU/GPU cores that dynamically reallocates bandwidth using buffer utilization information at runtime. As network traffic exhibits temporal and spatial fluctuations due to application behavior, SHARP can dynamically reallocate bandwidth and thereby adapt to application demands. SHARP demonstrates 34% performance (throughput) improvement over a baseline electrical CMESH while consuming 25% less energy per bit. Simulation results have also shown 6.9% to 14.9% performance improvement over other flavors of the proposed SHARP architecture without dynamic bandwidth allocation.

Rapid calculation of gravity anomalies based on residual node densities and its GPU implementation

Gravity forward modeling is an important part of three dimensional physical property inversion; however, its time-consuming nature restricts its practical application. Several authors have made efforts to develop this procedure and have achieved some success. This paper proposes a new simple and fast approach for computing gravity anomalies at arbitrary points. In our method, the subsurface is divided into a 3D array of rectangular prismatic blocks, each with a constant density. Then the block density model is transformed into a residual node density model. Finally, gravity anomalies at survey points are calculated using the new residual node density-based forward formula. This method is implemented on a CPU–GPU heterogeneous architecture with the CUDA FORTRAN language and achieves more than four times acceleration compared to the classical method in the same computational environment and two orders of magnitude acceleration compared to one CPU processor on synthetic random density model tests.

A GPU-based discrete element modeling code and its application in die filling

In this study, parallelization of a Discrete Element Method (DEM) code titled Trubal was carried out based on the CPU–GPU heterogeneous architecture where both two- and three-dimensional cases were assessed. In Trubal, the particle–particle/wall interaction rules are governed by the theoretical contact mechanics which enable the direct use of real physical material properties in the calculation. We reconstructed Trubal in two steps: reconstruction of the static storage structure; essential parallelism on the relative newer version code. Numerical simulations were implemented to present the benefits of this research. Firstly, two simulations of die filling with a moving shoe involving 6000 and 60,000 two-dimensional particles were conducted under (i) NVIDIA Tesla C2050 card together with Intel Core-Duo 2.93GHz CPU and (ii) NVIDIA Tesla K40c card along with Intel Xeon 3.00GHz CPU. Average speedups of (i) 4.69 and 12.78 as well as (ii) 6.52 and 18.60 in computational time were obtained, respectively. Then, a simulation of die filling with a stationary shoe containing 20,000 three-dimensional particles was carried out under the same conditions where average speedups of (i) 12.90 and (ii) 19.66 in computational time were obtained, respectively. It is shown that the final version parallel code gave a substantial acceleration on the original Trubal.

Design space exploration of on-chip ring interconnection for a CPU–GPU heterogeneous architecture

Incorporating a GPU architecture into CMP, which is more efficient with certain types of applications, is a popular architecture trend in recent processors. This heterogeneous mix of architectures will use an on-chip interconnection to access shared resources such as last-level cache tiles and memory controllers. The configuration of this on-chip network will likely have a significant impact on resource distribution, fairness, and overall performance.The heterogeneity of this architecture inevitably exerts different pressures on the interconnection due to the differing characteristics and requirements of applications running on CPU and GPU cores. CPU applications are sensitive to latency, while GPGPU applications require massive bandwidth. This is due to the difference in the thread-level parallelism of the two architectures. GPUs use more threads to hide the effect of memory latency but require massive bandwidth to supply those threads. On the other hand, CPU cores typically running only one or two threads concurrently are very sensitive to latency.This study surveys the impact and behavior of the interconnection network when CPU and GPGPU applications run simultaneously. Among our findings, we observed that significant interference exists between CPU and GPU applications and resource partitioning, in particular virtual and physical channel partitioning, shows effectiveness to solve the interference problem. Also, heterogeneous link configurations show promising results by optimizing traffic hotspots in the network. Finally, we evaluated different placement policies and found that how to place different components in the network significantly affects the performance. Based on these findings, we suggest an optimal ring interconnect network. Our study will shed light on other architectural interconnection studies on CPU–GPU heterogeneous architectures.