Coulomb Mobility Research Articles

Impact of Post-Trench Process Treatment on Electron Scattering Mechanisms in 4H-SiC Trench MOSFETs

This work reports the influence of post-trench treatment on electron scattering mechanisms in 4H-silicon carbide (SiC) trench MOSFETs. The mobilities representing different scattering mechanisms were extracted from the simulated transfer characteristics of devices with different post-trench Ar annealing conditions at temperatures of 0 °C–200 °C. Various mobilities, such as Coulomb mobility ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu _{\text {C}}{)}$ </tex-math></inline-formula> and surface roughness mobility ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu _{\text {SR}}{)}$ </tex-math></inline-formula> , were compared and analyzed in different samples at room temperature (RT). The result shows that accompanied by the sacrificial oxidation, Ar annealing at different temperatures and times (1500 °C and 5 min, 1500 °C and 15 min, and 1600 °C and 5 min) slightly influences Coulomb mobility but affects surface roughness mobility obviously. Further study has revealed that the Coulomb mobility is strongly related to the density of occupied interface traps, while the sidewall surface roughness gives rise to the change in surface roughness mobility.

Progress of the study on carrier scattering mechanisms of silicon/germanium field effect transistors

As the feature size of Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) continues to decrease, large numbers of new problems appear. Techniques such as strain project, new channel materials and new device structures are considered by academics and industry to be effective ways to continue to improve device performance. In this paper, the scattering mechanism of carriers in the device channel is studied from three aspects: strain technique, new channel material and new structure device: (1) strain technique: Biaxial tensile strain can change carrier distribution among different energy levels, which affects Coulomb scattering and Coulomb mobility. Furthermore, from the TEM image, it is found that biaxial tensile reduces the channel surface roughness for Si nMOSFET, leading an enhancement of electron mobility. However, no such similar phenomena were observed in pMOSFET. Based on this, a new method for calculating the mobility of MOSFET surface roughness scattering using TEM image has been proposed. (2) New channel material: In the germanium (Ge) transistors with different crystal faces, the scattering mechanisms of electron under high field conditions are different. The phonon scattering dominates the Ge(100) transistor, while the surface roughness scattering dominates the Ge(110), (111) transistors. This result is quite different from Si MOSFET. Therefore, a unified model for the scattering mechanism of electron in Ge nMOSFET has been proposed. In SiGe transistors, alloy scattering mainly play a role in the region with relatively small effective electric field (&lt;i&gt;E&lt;/i&gt;&lt;sub&gt;eff&lt;/sub&gt;). The strength of alloy scattering would be weakened in high field and could be decreased by reducing the thickness of SiGe layer. (3) New structure devices: In ultra-thin body germanium (GeOI) transistors, carrier transport is influenced by high- k /channel interfaces, as well as Ge channel/buried oxide (BOX) interface. As the Ge layer thickness decreases, carrier distribution is closer to the interfaces, which intensifies Coulomb scattering and surface roughness scattering. As a result, the mobility in GeOI transistor decreases as the thickness scaling. In addition, the distribution of electron in different energy valleys changes with the thickness decrease in Ge layer, which affects the scattering of electrons. When the Ge film is lower than 10 nm, a part of electron in the L valley will move to the Γ valley, causing the decrease of electron effective mass and increasing the electron mobility.

An analytical mobility model for square Gate-All-Around MOSFETs

A low-field mobility model for square GAA MOSFETs has been developed. The model is analytical and explicit, so it can be used in device simulators and, most importantly, in compact models of these Multi-gate devices for circuit simulation purposes. We have made use of a simulator that includes quantum effects to characterize the electron mobility of square GAA MOSFETs with different sizes for the usual gate voltages and operation regimes. The dependencies with the silicon core lateral size, the inversion charge and the surface roughness are included. The phonon, surface roughness and Coulomb mobility components are modeled separately by means of the Matthiessen rule. Finally, we have performed a comparison between our model and experimental results for validation purposes. We find that the experimental results are well reproduced by our model.

Temperature-Dependent Remote-Coulomb-Limited Electron Mobility in $\hbox{n}^{+}$-Polysilicon Ultrathin Gate Oxide nMOSFETs

Additional electron mobility due to remote scatterers in n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -polysilicon 1.65-nm gate oxide (SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) n-channel metal-oxide-semiconductor field-effect transistors is experimentally extracted at three different temperatures (i.e., 233, 263, and 298 K). The core of the extraction process consists of simulated temperature-dependent universal mobility curves and Matthiessen's rule in a mobility universality region. Resulting additional mobility for the first time experimentally exhibits a negative temperature coefficient, confirming interface plasmons in a polysilicon depletion region to be dominant remote Coulomb scatterers. We also present corroborative evidence as quoted in the literature, including: 1) calculated temperature-dependent remote Coulomb mobility due to ionized impurity atoms in a polysilicon depletion region; 2) experimentally assessed additional mobility at room temperature; and 3) simulated remote Coulomb mobility due to interface plasmons in a polysilicon depletion region as well as its temperature coefficient. Validity of Matthiessen's rule used in this paper is verified.

An in-depth simulation study of Coulomb mobility in ultra-thin-body SOI MOSFETs

A comprehensive study of Coulomb-limited mobility in ultra-thin-body SOI MOSFETs is presented. Mobility curves for structures with interfacial charges at the gate oxide–semiconductor interface, at the buried oxide–semiconductor interface and simultaneously at both interfaces are calculated by means of Monte Carlo simulations. Coulomb-limited mobility is then isolated applying Matthiessen's rule. It is shown that the Coulomb-limited mobility due to the charges placed simultaneously at both interfaces is just the superposition of the effects separately produced by the charges at each interface. We also show that the influence of the silicon layer thickness on Coulomb-limited mobility strongly depends on the interface where the charges are located; the influence of the charges at the buried oxide–semiconductor interface rapidly weakens as the silicon layer is made thicker, while if the charges are placed at the gate oxide–semiconductor interface, Coulomb-limited mobility is scarcely modified with the silicon layer thickness.

Simulation Study of Coulomb Mobility in Strained Silicon

This paper presents a detailed simulation analysis aimed at assessing and explaining the dependence on the biaxial strain of the Coulomb-limited mobility in n-type silicon MOSFETs. By using a model based on the momentum relaxation time (MRT) approximation, we first show that we can reproduce fairly well a wide set of published experimental data, and then, we use our model to discuss the dependence on the strain of the mobility limited by either interface states or substrate impurities. Different from the experiments, in the simulations, the MRT approach allows us to analyze the different mobility components without resorting to the Matthiessen's rule, whose use may result in large errors in the extracted mobility components. Our simulations indicate that the interface-state-limited mobility is reduced in strained devices; this is in qualitative agreement with the experiments, and we discuss its interpretation in terms of physically transparent arguments. Our analysis also suggests that the strain-induced changes of the substrate-impurity-limited mobility are instead very small, and we provide a clear interpretation of such a result. Recent experiments, however, have reported a strain-induced improvement of the substrate-impurity-limited mobility, which has been unavoidably extracted by using the Matthiessen's rule. We argue that the systematic errors produced by the Matthiessen's rule can help reconcile the simulation and the experimental results.

Investigation of Coulomb Mobility in Nanoscale Strained PMOSFETs

This paper provides an experimental assessment of Coulomb scattering mobility for advanced strained devices. By accurate short-channel mobility extraction, we examine the impact of process-induced uniaxial strain on Coulomb mobility in short-channel pMOSFETs. Our extracted Coulomb mobility shows very weak stress dependency at room temperature. This finding has also been verified in both long- and short-channel devices by the four-point wafer bending measurement. Therefore, in order to maximize the process-induced strain efficiency on nanoscale pMOSFETs, lower surface impurity concentration is suggested to avoid the Coulomb mobility domination in carrier transport.

Impact of Process-Induced Strain on Coulomb Scattering Mobility in Short-Channel n-MOSFETs

This letter provides an experimental assessment of Coulomb scattering mobility for advanced short-channel strained devices. By accurate mobility extraction under various temperatures, we examine the impact of process-induced uniaxial strain on Coulomb mobility in short-channel nMOSFETs. This letter indicates that the Coulomb mobility has significant stress dependency. Moreover, the stress sensitivity of the Coulomb mobility shows strong temperature dependence. Because it is the interface scattering that counteracts the stress sensitivity of the bulk-impurity-limited mobility, further reducing the interface charges will be crucial to future mobility scaling.

Mobility Modeling and Its Extraction Technique for Manufacturing Strained-Si MOSFETs

A new mobility model, together with its extraction method for manufacturing strained-Si MOSFETs, is presented. An accurate mobility extraction is obtained from the linear drain current by excluding the parasitic source/drain resistance and the parasitic gate capacitance. In addition to universal curves, the Coulomb mobility is dependent on whether devices have compressive or tensile stress. The dependences of Coulomb scattering on different stress conditions can be decoupled from the effective channel mobility in Matthiessen's form. From the extracted results, the tensile-stress N-channel MOSFETs have less Coulomb scattering effect, while the compressive counterparts suffer the worse Coulomb mobility degradation. By including the Coulomb scattering corrections, our model can properly predict mobility enhancements for various strained-Si technologies and dimensions.

Numerical and experimental characterization of 4H-silicon carbide lateral metal-oxide-semiconductor field-effect transistor

Combined simulation and experimental analyses are performed to characterize the 4H-silicon carbide (SiC) lateral metal-oxide-semiconductor field-effect transistor (MOSFET). Using a quasi-two-dimensional depth dependent Coulomb mobility model for scattering due to interface and oxide charge, along with existing models for other scattering mechanisms, and an in-house drift diffusion device simulator tailored for SiC MOSFETs, we have extracted values for interface trap density of states for 4H-SiC MOSFETs. Characterization shows that the interface trapped charge in 4H-SiC MOSFETs is responsible for mobility degradation and reduction in mobile inversion charge, and therefore reduced current. Its effect on mobility degradation decreases at higher gate voltages due to increased screening. Our results show that at high gate voltages, surface roughness plays the major role in surface mobility degradation in 4H-SiC MOSFETs. Results indicate that due to high Coulomb scattering near the interface, current density is maximum a few nanometers away from the surface. The model indicates overall mobility values of approximately 20cm2∕Vs at the interface, and increasing to approximately 250cm2∕Vs near the bottom of the inversion layer. Simulations predict that tenfold reduction in interface and fixed oxide charge density would give rise to very favorable device characteristics.

An accurate Coulomb mobility model for MOS inversion layer and its application to NO-oxynitride devices

In this paper, a new mobility model for device simulation is presented that incorporates Coulomb scattering due to ionized impurities in the MOS inversion layer. It is well known that the Coulomb scattering strongly depends on carrier concentration because of the screening effect. A crucial technique is used in the modeling procedure, with which a local dependency of the mobility on carrier concentration is derived from the experimental data of the effective mobility. Consequently, the present model has the ability to reproduce the experimental effective mobility over a wide range of impurity concentration with a single parameter set. Comparisons of the simulated and measured I/sub DS/-V/sub GS/ curves show good agreement for 0.15 /spl mu/m CMOS devices having pure SiO/sub 2/ and NO-based oxynitride gate oxides.