Mask Cost Research Articles

Post-Quantum Authenticated Encryption against Chosen-Ciphertext Side-Channel Attacks

Over the last years, the side-channel analysis of Post-Quantum Cryptography (PQC) candidates in the NIST standardization initiative has received increased attention. In particular, it has been shown that some post-quantum Key Encapsulation Mechanisms (KEMs) are vulnerable to Chosen-Ciphertext Side-Channel Attacks (CC-SCA). These powerful attacks target the re-encryption step in the Fujisaki-Okamoto (FO) transform, which is commonly used to achieve CCA security in such schemes. To sufficiently protect PQC KEMs on embedded devices against such a powerful CC-SCA, masking at increasingly higher order is required, which induces a considerable overhead. In this work, we propose to use a conceptually simple construction, the ΕtS KEM, that alleviates the impact of CC-SCA. It uses the Encrypt-then-Sign (EtS) paradigm introduced by Zheng at ISW ’97 and further analyzed by An, Dodis and Rabin at EUROCRYPT ’02, and instantiates a postquantum authenticated KEM in the outsider-security model. While the construction is generic, we apply it to the CRYSTALS-Kyber KEM, relying on the CRYSTALSDilithium and Falcon signature schemes. We show that a CC-SCA-protected EtS KEM version of CRYSTALS-Kyber requires less than 10% of the cycles required for the CC-SCA-protected FO-based KEM, at the cost of additional data/communication overhead. We additionally show that the cost of protecting the EtS KEM against fault injection attacks, necessarily due to the added signature verification, remains negligible compared to the large cost of masking the FO transform at higher orders. Lastly, we discuss relevant embedded use cases for our EtS KEM construction.

A template-free, more environmentally friendly approach for glass micro-texturing

Micron and nanometer size textured silicate glass surfaces are of interest in consumer electronics, photovoltaics, and biosensing applications. Typically, texturing glass surfaces requires applying a patterned mask or a pre-etching treatment (e.g. sandblasting) on the glass substrate, followed by a mask transferring or etching process using a fluoride-containing compound. The major challenges of such a process are the complexity and cost of masking, and the safety and environmental concerns around the usage and disposal of hydrofluoric acid. Here, we describe a template-free method to construct micron-sized and submicron-sized texture on isotropic glass surfaces in one step. The new texturing mechanisms are well supported by experimental data and peridynamic simulations. With this novel strategy, the etchant uses fluoride-free chemicals such as citric acid to texture silicate glass. Etchant concentration, etch temperature, time, and additives are the primary parameters that dictate the texturing process. Surface feature size and depth can be independently controlled by tuning the leaching and chemical polishing process. We hope this study can trigger more research on novel and more environmentally friendly texturing of isotropic materials.

A secure and highly efficient first-order masking scheme for AES linear operations

Due to its provable security and remarkable device-independence, masking has been widely accepted as a noteworthy algorithmic-level countermeasure against side-channel attacks. However, relatively high cost of masking severely limits its applicability. Considering the high tackling complexity of non-linear operations, most masked AES implementations focus on the security and cost reduction of masked S-boxes. In this paper, we focus on linear operations, which seems to be underestimated, on the contrary. Specifically, we discover some security flaws and redundant processes in popular first-order masked AES linear operations, and pinpoint the underlying root causes. Then we propose a provably secure and highly efficient masking scheme for AES linear operations. In order to show its practical implications, we replace the linear operations of state-of-the-art first-order AES masking schemes with our proposal, while keeping their original non-linear operations unchanged. We implement four newly combined masking schemes on an Intel Core i7-4790 CPU, and the results show they are roughly 20% faster than those original ones. Then we select one masked implementation named RSMv2 due to its popularity, and investigate its security and efficiency on an AVR ATMega163 processor and four different FPGA devices. The results show that no exploitable first-order side-channel leakages are detected. Moreover, compared with original masked AES implementations, our combined approach is nearly 25% faster on the AVR processor, and at least 70% more efficient on four FPGA devices.

De l'utilité de l'impôt pour freiner l'effet de levier du « hors-bilan » des banques

Les normes comptables IFRS ont intégré dans le bilan des banques l'essentiel des instruments financiers dérivés que nous considérons ici sous le terme de « hors-bilan », au prix d'une certaine invisibilité de leur « effet de levier ». Nous décrivons l'activité des banques de financement et d'investissement et montrons que ces instruments dérivés correspondent à une fonction d'intermédiation du risque dans l'économie où les banques ne « portent » pas ce risque au bilan, contrairement au métier bancaire traditionnel de « transformation ». Nous décrivons la banque comme une source d'« accroissement des possibles de la taille du marché » que nous définissons au préalable d'une manière générale. Une telle source, comme toute innovation, est synonyme de risque. Le « hors-bilan » bancaire apparaît dans ce cadre comme un effet de levier sans limite naturelle. Nous étudions alors ce que pourraient être des fiscalités adaptées à trois objectifs différents : corriger et capter les rentes, limiter le risque systémique, maîtriser l'« accroissement des possibles ». Une assiette considérant une mesure des engagements en valeur absolue associés aux positions sur les produits dérivés, dans le bilan des banques, paraît pertinente pour limiter l'accroissement des possibles et, partant de là, le risque. Classification JEL : G21, G32, G38.

Mask Cost and Profitability in Photomask Manufacturing: An Empirical Analysis

An empirical study of the economics of manufacturing photomasks concludes that the uncontrolled growth of optical proximity effect correction and resolution enhancement techniques is driving up the cost of pattern generation and mask inspection to levels that threaten the profitability of photomask manufacturing. The intrinsic cost of some leading edge photomasks has already exceeded the price that customers are willing to pay for them. A model of the lifecycle of photomask manufacturing, developed from interviews involving the 1990-to-2005 operations of six mask shops and a survey of seven photomask manufacturers, shows that design for manufacturability (DFM) constitutes the most promising approach for alleviating this market impasse. Unilateral action by mask shops to increase their capital productivity is necessary but insufficient and perhaps unaffordable. DFM solutions will require the majority of participants in the lithography value chain to collaborate according to a volatile demand schedule that is driven by semiconductor manufacturers

Cut-price tricks for custom chip masks

Mask costs seem to be putting ASICs out of reach of many users, but there are ways to make big savings on masks - as long as the other trade-offs work for you.

Redundancy design for a fault tolerant systolic array

A systematic design methodology for redundant systolic arrays is proposed. Redundancies consisting of space-shift, time-shift and space-time-shift schemes are applied successfully to detect or mask permanent faults, transient faults or both. Various redundancy designs for different utilisation efficiencies of processor elements can be obtained at the design stage by a dependent graph and its associated algebraic transformation. A customised optimal redundant systolic array design can be achieved for various performance requirements, including throughput rate, latency, average computation time, hardware cost and capabilities of fault detection and fault masking.