Cost-effective Chip Research Articles

Development of fin-LEDs for next-generation inorganic displays using face-selective dielectrophoretic assembly

Micro-light-emitting diodes offer vibrant colors and energy-efficient performance, holding promise for next-generation inorganic displays. However, their widespread adoption requires the development of cost-effective chips and low-defect pixelation processes. Addressing these challenges, nanorod-light-emitting diodes utilize inkjet and dielectrophoretic assembly techniques. Nevertheless, the small volume and edge-directed emission of nanorod-light-emitting diodes necessitate brightness and light extraction improvements. As an alternative, we propose dielectrophoretic-friendly fin-light-emitting diodes, designed to enhance brightness and light extraction efficiency through face-selective dielectrophoretic assembly technology. Our results confirm the potential for next-generation inorganic displays, with a wafer utilization ratio exceeding 90%, a vertical assembly ratio of 91.3%, and a pixel production yield of 99.93%. Moreover, blue fin-light-emitting diodes achieve an external quantum efficiency of 9.1% and a brightness of 8640 cd m−2 at 5.0 V, which, even at this early stage, are comparable to existing technologies.

Electrochemical immunosensor for detection of CA 15-3 biomarker in point-of-care

This work reports the development of a simple and rapid electrochemical immunosensor for the determination of breast cancer biomarker Cancer Antigen 15–3 (CA 15–3). Disposable and cost-effective chips, consisting of gold screen-printed electrodes (AuSPEs), were used to develop the portable electrochemical devices for monitoring the biomarker in point-of-care (PoC), under clinical context.The biosensor preparation consisted of two simple steps. First, a self-assembled monolayer (SAM) of mercaptosuccinic acid (MSA) was formed at the AuSPE surface. Then, the CA 15–3 antibody was covalently bound to the carboxylic groups standing at the electrode surface using EDC/NHS chemistry.The performance of the developed immunosensor was evaluated by assessing the sensor sensitivity, linear response interval, selectivity and detection limit (LOD). The developed immunosensor provided a wide linear concentration range (from 1.0 to 1000 U mL−1) and low detection levels were achieved (LOD of 0.95 U mL−1), enabling the sensitive detection of the cancer biomarker at clinically relevant levels, using square wave voltammetry (SWV) as electroanalytical technique. Moreover, selectivity studies performed against other cancer biomarkers (CA 125 and CA 19–9) revealed that the antibody has high selectivity for CA 15–3 antigen. The immunosensor was applied to the quantification of CA 15–3 in artificial serum samples with satisfactory results.

Short-Term Field Performance and Cost-Effectiveness of Crumb-Rubber Modified Asphalt Emulsion in Chip Seal Applications

Chip sealing is a commonly used pavement maintenance technique that aims to delay pavement deterioration by reducing water infiltration and restoring skid resistance. The objective of this study was to evaluate the short-term field performance and cost-effectiveness of chip seals prepared with different types of asphalt emulsion and application rates. A newly introduced crumb-rubber modified asphalt emulsion was evaluated, one that allows chip seal installation at the same temperature as a standard emulsion. Types of emulsion included a crumb-rubber modified asphalt emulsion (CRS-2TR), a polymer-modified emulsion (CRS-2P), and a conventional unmodified emulsion (CRS-2). Application rates were obtained from the Louisiana Department of Transportation and Development (DOTD), the Texas Department of Transportation (DOT) specifications, and from the chip seal design method recommended in NCHRP Report 680. Seven chip seal sections were constructed and monitored regularly over a 12-month period. In the northbound lane, the chip seal section constructed with CRS-2TR (0.37 gal per square yard [gsy]) was the best performer statistically. In the southbound lane, the chip seal sections constructed with CRS-2TR and CRS-2P (0.31 gsy) performed similarly. Furthermore, the maximum Service Life Extension (SLE) was observed for the CRS-2TR (0.31 gsy) chip seal sections, whereas the chip seal sections constructed with CRS-2 had the lowest SLE. In addition, the most cost-effective chip seal section was achieved by the application of CRS-2TR emulsion at the Louisiana DOTD recommended emulsion application rate.

On-the-fly Computation Method in Field-Programmable Gate Array for Analog-to-Digital Converter Linearity Testing

This paper presents a new approach to linearity testing of analog-to-digital converters (ADCs) through on-the-fly computation in field-programmable gate array (FPGA) hardware. The proposed method computes the linearity while it is processing without compromising the accuracy of the measurement, so very little overhead time is required to compute the final linearity. The results will be displayed immediately after a single ramp is supplied to the device under test. This is a cost-effective chip testing solution for semiconductor companies, achieved by reducing computing time and utilization of low-cost and low-specification automatic test equipment (ATE). The experimental results showed that the on-the-fly computation method significantly reduced the computation time (up to 44.4%) compared to the conventional process. Thus, for every 100M 12-bit ADC tested with 32 hits per code, the company can save up to 139,972 Php on electricity consumption.

Image sensors go broadband

The demonstration of a quantum dot-sensitized graphene image sensor that offers a very broad spectral response and that is integrated with silicon CMOS technology could potentially be a new cost-effective chip platform for hyperspectral imaging and spectroscopy.

Thirty Gigahertz Optoelectronic Mixing in Chemical Vapor Deposited Graphene.

The remarkable properties of graphene, such as broadband optical absorption, high carrier mobility, and short photogenerated carrier lifetime, are particularly attractive for high-frequency optoelectronic devices operating at 1.55 μm telecom wavelength. Moreover, the possibility to transfer graphene on a silicon substrate using a complementary metal-oxide-semiconductor-compatible process opens the ability to integrate electronics and optics on a single cost-effective chip. Here, we report an optoelectronic mixer based on chemical vapor-deposited graphene transferred on an oxidized silicon substrate. Our device consists in a coplanar waveguide that integrates a graphene channel, passivated with an atomic layer-deposited Al2O3 film. With this new structure, 30 GHz optoelectronic mixing in commercially available graphene is demonstrated for the first time. In particular, using a 30 GHz intensity-modulated optical signal and a 29.9 GHz electrical signal, we show frequency downconversion to 100 MHz. These results open promising perspectives in the domain of optoelectronics for radar and radio-communication systems.

Measurement of Pavement Treatment Macrotexture and Its Effect on Bicycle Ride Quality

This paper summarizes the results of measurements of macrotexture on a set of California Department of Transportation (Caltrans) and local government pavement surface treatments and their correlation with survey results of bicycle vibration and ride quality on the same sections. The test sections that were used for the bicycle vibration and ride quality measurements included various surface treatments placed on an existing chip seal on SR-198 in Monterey County, a chip seal on SR-1 in San Luis Obispo County, and several other sections with various textures and roughness levels on other state highway and county road sections. Macrotexture was measured in mean profile depth (MPD). Three test methods were used to measure MPD: the sand patch, the laser texture scanner, and the inertial profiler. Presented are statistical correlations between macrotexture, roughness [according to the international roughness index (IRI)], bicycle vibration, and bicycle ride quality for the surveyed treatment sections. Conclusions are presented for MPD values measured on road sections with different treatment designs and for the variability of MPD found between sections built with the same chip seal aggregate grading. Correlations between bicycle vibration and MPD are presented, along with correlations between MPD, IRI, bicycle vibration, and bicyclists' perception of ride quality and pavement acceptability for bicycle use. This study's results can assist Caltrans and other road owners considering gradation when continuing to use the cost-effective chip seal treatment to preserve their pavements while maintaining a bicycle-friendly surface.

A Signal Generator Based on AD9850

This paper analyzes the advantages of the direct digital frequency synthesis (DDS) in signal generator applications, introduces the basic principles and characteristics of AD9850, a cost-effective chip, shows the overall scheme of a signal source design based on DDS and implements the hardware system. Experimental results show the signal generator can produce sine wave signals scoping from 100Hz to 5MHz, clock signals and triangular wave signals and can display frequency on the LCD.

A CMOS Low-Power Digital Polar Modulator System Integration for WCDMA Transmitter

This paper presents a novel low-power design and highly cost effective chip implementation solution of digital polar modulator for WCDMA transmitters using 0.35 μm mixed mode CMOS technology. The proposed coordinate rotation digital computer (CORDIC) in the polar modulator converts rectangular coordinate to polar coordinate with significantly less hardware and power comparing to the existing computational intensive algorithm by employing hard wired pipeline strategy to increase the performance and to reduce the hardware size. The proposed CORDIC performs a sequence of elementary rotations using shift and add operations without multiplications, providing a highly cost effective solution. The separate distribution of angle constants to each adder permits a hard-wire solution instead of using a lookup table, and all the shifters are hard-wired. Linear interpolators to extend the sampling rate for WCDMA specification are used to decrease the operating frequency. The proposed approach reduces both size and power by integrating booth CORDIC and power amplifier on the same die. The measured average power consumption is 27 mW with 67 MHz clock and 3 V power supply.

Encapsulation of ISFET sensor chips

The encapsulation of ISFET sensor chips is a challenge to sensor technology and materials. Recently developed new packaging technologies enable reliable and cost effective chip encapsulation. By this, one of the serious problems, which had hindered the large-scale production and industrial application of ISFET sensors over three decades could be overcome now to a large extent. The paper reports both on ISFET encapsulation methods on laboratory level and advanced industrial production technologies. The influence of the packaging design on special applications and on the dynamic behaviour of the sensor is illustrated. Furthermore, sensor materials are characterised and various testing methods are described.

Encapsulation of ISFET sensor chips

The encapsulation of ISFET sensor chips is a challenge to sensor technology and materials. Recently developed new packaging technologies enable reliable and cost effective chip encapsulation. By this, one of the serious problems, which had hindered the large-scale production and industrial application of ISFET sensors over three decades could be overcome now to a large extent. The paper reports both on ISFET encapsulation methods on laboratory level and advanced industrial production technologies. The influence of the packaging design on special applications and on the dynamic behaviour of the sensor is illustrated. Furthermore, sensor materials are characterised and various testing methods are described.

A cost-effective three-step hierarchical search block-matching chip for motion estimation

A dedicated cost-effective chip of a three-step hierarchical search (3SHS) motion estimator to support the NTSC resolution video in real time is proposed. The memory interleaving technique is developed to overcome the 3SHS's inherent problem of complicated data addressing and interconnection due to the variable distance between candidate locations and unpredictable data requirements. Based on a cyclic-pipeline utilization of memory, the memory size and bandwidth requirements can be reduced significantly. With 0.8 /spl mu/m CMOS technology, the proposed chip requires a die size of 6.9/spl times/5.9 mm/sup 2/ with 120 K transistors, and is able to operate at a clock rate of more than 50 MHz.

Advanced Digital Television System

This paper will give an architectural overview of an advanced digital televisicn system which utilizes the latest VISI technology, fast digital signal proessing ard frame buffer. This digital design aproach will lead to a cost-effective chip set that will produce improved quality, and higher definition TV picture for either the NTSC or PAL system.