Cortex-M Family Research Articles

Monocular Depth Perception on Microcontrollers for Edge Applications

Depth estimation is crucial in several computer vision applications, and a recent trend in this field aims at inferring such a cue from a single camera. Unfortunately, despite the compelling results achieved, state-of-the-art monocular depth estimation methods are computationally demanding, thus precluding their practical deployment in several application contexts characterized by low-power constraints. Therefore, in this paper, we propose a lightweight Convolutional Neural Network based on a shallow pyramidal architecture, referred to as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> PyD-Net, enabling monocular depth estimation on microcontrollers. The network is trained in a peculiar self-supervised manner leveraging proxy labels obtained through a traditional stereo algorithm. Moreover, we propose optimization strategies aimed at performing computations with quantized 8-bit data and map the high-level description of the network to low-level layers optimized for the target microcontroller architecture. Exhaustive experimental results on standard datasets and an in-depth evaluation with a device belonging to the popular Arm Cortex-M family confirm that obtaining sufficiently accurate monocular depth estimation on microcontrollers is feasible. To the best of our knowledge, our proposal is the first one enabling such remarkable achievement, paving the way for the deployment of monocular depth cues onto the tiny end-nodes of distributed sensor networks.

Atrial Fibrillation Detection on Low-Power Wearables using Knowledge Distillation.

The increasing complexity and memory requirements of neural networks have been slowing down the adoption of AI in low-power wearable devices, which impose important restrictions in computational power and memory footprint. These low-power systems are the key to obtain 24/7 monitoring systems necessary for the current personalized healthcare trend since they do not require constant charging. In this work, we apply Knowledge Distillation to our previously published convolutional-recurrent neural network for cardiac arrhythmia detection and classification. We show that the resulting network halves the memory footprint (138 K parameters) and the number of operations (1.84 MOp) compared to the baseline. By using Knowledge Distillation, this network also achieves significantly higher accuracy after quantization (increase in overall F1 score from 0.779 to 0.828) and is capable of running into a nRF52832 System-on-Chip from Nordic Semiconductors. This promising result lays the groundwork for deployment on resource-constrained embedded platforms such as micro-controllers of the ARM Cortex-M family, thus potentially enabling continuous detection of cardiac arrhythmias in low-power wearable devices.

Fast and Accurate Inference on Microcontrollers With Boosted Cooperative Convolutional Neural Networks (BC-Net)

Arithmetic precision scaling is mandatory to deploy Convolutional Neural Networks (CNNs) on resource-constrained devices such as microcontrollers (MCUs), and quantization via fixed-point or binarization are the most adopted techniques today. Despite being born by the same concept of bit-width lowering , these two strategies differ substantially each other, and hence are often conceived and implemented separately. However, their joint integration is feasible and, if properly implemented, can bring to large savings and high processing efficiency. This work elaborates on this aspect introducing a boosted collaborative mechanism that pushes CNNs towards higher performance and more predictive capability. Referred as BC-Net , the proposed solution consists of a self-adaptive conditional scheme where a lightweight binary net and an 8-bit quantized net are trained to cooperate dynamically. Experiments conducted on four different CNN benchmarks deployed on off-the-shelf boards powered with the MCUs of the Cortex-M family by ARM show that BC-Nets outperform classical quantization and binarization when applied as separate techniques (up to 81.49% speed-up and up to 3.8% of accuracy improvement). The comparative analysis with a previously proposed cooperative method also demonstrates BC-Nets achieve substantial savings in terms of both performance (+19%) and accuracy (+3.45%).

FANN-on-MCU: An Open-Source Toolkit for Energy-Efficient Neural Network Inference at the Edge of the Internet of Things

The growing number of low-power smart devices in the Internet of Things is coupled with the concept of "Edge Computing", that is moving some of the intelligence, especially machine learning, towards the edge of the network. Enabling machine learning algorithms to run on resource-constrained hardware, typically on low-power smart devices, is challenging in terms of hardware (optimized and energy-efficient integrated circuits), algorithmic and firmware implementations. This paper presents FANN-on-MCU, an open-source toolkit built upon the Fast Artificial Neural Network (FANN) library to run lightweight and energy-efficient neural networks on microcontrollers based on both the ARM Cortex-M series and the novel RISC-V-based Parallel Ultra-Low-Power (PULP) platform. The toolkit takes multi-layer perceptrons trained with FANN and generates code targeted at execution on low-power microcontrollers either with a floating-point unit (i.e., ARM Cortex-M4F and M7F) or without (i.e., ARM Cortex M0-M3 or PULP-based processors). This paper also provides an architectural performance evaluation of neural networks on the most popular ARM Cortex-M family and the parallel RISC-V processor called Mr. Wolf. The evaluation includes experimental results for three different applications using a self-sustainable wearable multi-sensor bracelet. Experimental results show a measured latency in the order of only a few microseconds and a power consumption of few milliwatts while keeping the memory requirements below the limitations of the targeted microcontrollers. In particular, the parallel implementation on the octa-core RISC-V platform reaches a speedup of 22x and a 69% reduction in energy consumption with respect to a single-core implementation on Cortex-M4 for continuous real-time classification.

Abstract timers and their implementation onto the ARM Cortex-M family of MCUs

Real-Time For the Masses (RTFM) is a set of languages and tools being developed to facilitate embedded software development and provide highly efficient implementations geared to static verification. The RTFM-kernel is an architecture designed to provide highly efficient and predicable Stack Resource Policy based scheduling, targeting bare metal (single-core) platforms. We contribute by introducing a platform independent timer abstraction that relies on existing RTFM-kernel primitives. We develop two alternative implementations for the ARM Cortex-M family of MCUs: a generic implementation, using the ARM defined SysTick/DWT hardware; and a target specific implementation, using the match compare/free running timers. While sacrificing generality, the latter is more flexible and may reduce overall overhead. Invariants for correctness are presented, and methods to static and run-time verification are discussed. Overhead is bound and characterized. In both cases the critical section from release time to dispatch is less than 2us on a 100MHz MCU. Queue and timer mechanisms are directly implemented in the RTFM-core language ( -core in the following) and can be included in system-wide scheduling analysis.

Performance evaluation of CMSIS-RTOS: benchmarks and comparison

The CMSIS-RTOS standard, recently published by ARM, defines a real-time operating system application programming interface (RTOS API) for lower-end microcontrollers. The benefits of such a standard include the improvement of portability among microcontroller applications, the incentive to the market of standardised middleware libraries, and the acceleration of the learning curve for RTOS-users. CMSIS-RTOS was designed for the ARM Cortex-M family of 32-bit RISC microcontrollers but its applicability encompasses the full range of lower-end microcontrollers. The target hardware platform of CMSIS-RTOS encompasses a different range than those where the POSIX standard is applicable. Compliance with the CMSIS-RTOS standard can be achieved by design, which is the case for new RTOSes, or by an adaptation layer on top of an existing RTOS. The performance evaluation conducted in this research covers both cases. The research question is: 'Does compliance with the CMSIS-RTOS standard impose a performance penalty?'. This is the first reported research to conduct a performance evaluation of CMSIS-RTOS; the results presented here indicate that compliance with the CMSIS-RTOS standard does not impose a performance penalty.