Core Graph Research Articles

Research on Path Planning Method based on Graph Search Algorithm

Path planning, crucial in robotics and autonomous vehicles, involves finding efficient routes from start to finish while avoiding obstacles. Graph search algorithms like BFS, DFS, and A* are commonly used for this purpose. This research focuses on analyzing these algorithms' performance and applicability in diverse scenarios. The study provides a comprehensive overview of path planning's definition, application domains, and fundamental principles. It then delves into the core graph search algorithms: BFS explores nodes layer by layer, ensuring the shortest path is found first but suffering from high time complexity. DFS explores nodes in a depth-first manner, potentially leading to shorter paths but risking getting trapped in local optima. In contrast, A* combines the strengths of BFS and DFS by using heuristic functions to guide the search for the cheapest path to the goal. Despite their utility, graph search algorithms have limitations. The high time complexity of A* in large-scale environments and the potential for local optima are key challenges. To address these, research explores improved methods like GBFS and bidirectional A* search. The future direction of research includes developing more efficient heuristic functions, exploring hybrid algorithms, parallelizing path planning, and applying these methods to new domains like autonomous drones and self-driving cars. This research paves the way for more robust and efficient path planning algorithms in various applications.

Unbiased pangenome graphs.

Pangenome variation graphs model the mutual alignment of collections of DNA sequences. A set of pairwise alignments implies a variation graph, but there are no scalable methods to generate such a graph from these alignments. Existing related approaches depend on a single reference, a specific ordering of genomes or a de Bruijn model based on a fixed k-mer length. A scalable, self-contained method to build pangenome graphs without such limitations would be a key step in pangenome construction and manipulation pipelines. We design the seqwish algorithm, which builds a variation graph from a set of sequences and alignments between them. We first transform the alignment set into an implicit interval tree. To build up the variation graph, we query this tree-based representation of the alignments to reduce transitive matches into single DNA segments in a sequence graph. By recording the mapping from input sequence to output graph, we can trace the original paths through this graph, yielding a pangenome variation graph. We present an implementation that operates in external memory, using disk-backed data structures and lock-free parallel methods to drive the core graph induction step. We demonstrate that our method scales to very large graph induction problems by applying it to build pangenome graphs for several species. seqwish is published as free software under the MIT open source license. Source code and documentation are available at https://github.com/ekg/seqwish. seqwish can be installed via Bioconda https://bioconda.github.io/recipes/seqwish/README.html or GNU Guix https://github.com/ekg/guix-genomics/blob/master/seqwish.scm.

The Effects of Climate Change on Habitat Connectivity: A Case Study of the Brown-Eared Pheasant in China

Climate change has caused habitat fragmentation and reduced connectivity. The Fen River Basin in Shanxi Province, China is an important habitat for the central population of the brown-eared pheasant (BEP). The effects of climate change need to be considered in the conservation planning of BEP habitats. We used a species dispersion model to determine the BEP core habitat and graph theory to explore the connectivity of the BEP’s main habitats. The pinch point areas of BEP dissemination were determined by circuit theory. Least-cost pathways were used to identify the critical corridors for BEP dissemination. A gap analysis was conducted to estimate the efficiency of BEP conservation measures. Under the future climate scenarios, BEP habitats decreased by between 54.69% and 97.63%, and the connectivity of the main habitats was reduced by a similar magnitude. The BEP core habitat shifted to the southwestern region under the influence of climatic conditions. Currently, 90.84% of the species’ critical habitat remains unprotected. Due to climate change, the core habitat in the future was projected to differ from the current protected area. Enhancing the protection of the pinch point region may aid in the restoration of habitat connectivity.

A new density core graph-cut class decomposition to improve neural network classification performance

<span>This research presents a new pre-processed class decomposition technique called density core graph-cut (DCGC). The method uses supervised clustering instead of a traditional unsupervised one to decompose the class. Supervised clustering requires additional label information to function and with that it gains a better understanding of the distribution. DCGC employs nearest neighbors to form a density core graph for each class. Then, the edges of each graph to be removed or cut is identified utilizing class information. Lastly, it yields final clusters by grouping all connected cores and assigning the remaining samples to a cluster where the nearest core belongs. Training neural network classifiers on complex label data will yield a better accuracy with the modified class representation. Intuitively, the decision boundaries separating classes based on the modified labels are less complex, and classifiers’ chance to reach these hyperplanes is higher. The results present that training neural networks using label representations from DCGC significantly helps improve the classification accuracy of neural networks on syntactic datasets as high as 30%. For real-world problems, the experiment presents a mixed result in which some datasets moderately benefit from DCGC.</span>

Querying RDF Databases with Sub-CONSTRUCTs

Graph query languages feature mainly two kinds of queries when applied to a graph database: those inspired by relational databases which return tables such as SELECT queries and those which return graphs such as CONSTRUCT queries in SPARQL. The latter are object of study in the present paper. For this purpose, a core graph query language GrAL is defined with focus on CONSTRUCT queries. Queries in GrAL form the final step of a recursive process involving so-called GrAL patterns. By evaluating a query over a graph one gets a graph, while by evaluating a pattern over a graph one gets a set of matches which involves both a graph and a table. CONSTRUCT queries are based on CONSTRUCT patterns, and sub-CONSTRUCT patterns come for free from the recursive definition of patterns. The semantics of GrAL is based on RDF graphs with a slight modification which consists in accepting isolated nodes. Such an extension of RDF graphs eases the definition of the evaluation semantics, which is mainly captured by a unique operation called Merge. Besides, we define aggregations as part of GrAL expressions, which leads to an original local processing of aggregations.

GraphMineSuite

We propose GraphMineSuite (GMS): the first benchmarking suite for graph mining that facilitates evaluating and constructing high-performance graph mining algorithms. First, GMS comes with a benchmark specification based on extensive literature review, prescribing representative problems, algorithms, and datasets. Second, GMS offers a carefully designed software platform for seamless testing of different fine-grained elements of graph mining algorithms, such as graph representations or algorithm subroutines. The platform includes parallel implementations of more than 40 considered baselines, and it facilitates developing complex and fast mining algorithms. High modularity is possible by harnessing set algebra operations such as set intersection and difference, which enables breaking complex graph mining algorithms into simple building blocks that can be separately experimented with. GMS is supported with a broad concurrency analysis for portability in performance insights, and a novel performance metric to assess the throughput of graph mining algorithms, enabling more insightful evaluation. As use cases, we harness GMS to rapidly redesign and accelerate state-of-the-art baselines of core graph mining problems: degeneracy reordering (by >2X), maximal clique listing (by >9×),k-clique listing (by up to 1.1×), and subgraph isomorphism (by 2.5×), also obtaining better theoretical performance bounds.

Finding Critical Users in Social Communities via Graph Convolutions

Finding critical users in social networks is an important issue. The criticalness of a user can be measured by the number of followers who will leave the community together when the user leaves. By taking a social community as a k-core, the problem of finding critical users is to find a set of nodes, U, of size b in a k-core that maximizes the number of nodes to be deleted from the k-core when all nodes in U are deleted. This problem is NP-hard. The state-of-the-art greedy algorithm is with no guarantee on the set of nodes U found. In this paper, we propose a neural network model, called Self-attentive Core Graph Convolution Network (SCGCN), to capture the hidden structure of the criticalness among node combinations that break the engagement of a specific social community. Supervised by sampling node combinations, SCGCN has the ability to inference the criticalness of unseen combinations of nodes. To further reduce the sampling and inference space, we propose a deterministic strategy to prune unpromising nodes on the graph. Our experiments conducted on many real-world graphs show that SCGCN significantly improves the quality of the solution compared with the state-of-the-art greedy algorithm.

Application-Specific SoC Design Using Core Mapping to 3D Mesh NoCs with Nonlinear Area Optimization and Simulated Annealing

Core mapping, in which a core graph is mapped to a network graph to minimize communication, is a common design problem for Systems-on-Chip interconnected by a Network-on-Chip. In conventional multiprocessors, this mapping is area-agnostic as the cores in the core graph are uniform and therefore iso-area. This changes for Systems-on-Chip because tasks are mapped to specific blocks and not general-purpose cores. Thus, the area of these specific cores is varying. This requires novel mapping methods. In this paper, we propose a an area-aware cost function for simulated annealing; Furthermore, we advocate the use of nonlinear models as the area is nonlinear: A semi-definite program (SDP) can be used as it is sufficiently fast and shows 20% better area than conventional linear models. Our cost function allows for up to 16.4% better area, 2% better communication (bandwidth times hop distance) and 13.8% better total bandwidth in the network in comparison to the standard approach that accounts for both the network communication and uses cores with varying areas as well.

A Reliability-Aware Joint Design Method of Application Mapping and Wavelength Assignment for WDM-Based Silicon Photonic Interconnects on Chip

Silicon photonic interconnects on chip is an emerging technology for future ultra-scale and data-intensive computing chips, e.g., many-core processors, owing to its high transmission speed and low latency. However, in the Wavelength Division Multiplexing (WDM)-based architecture, the communication reliability can be significantly affected by the signal losses and crosstalk, due to the inherent characteristic of photonic devices. This paper studies the influence on reliability of managing application mapping and wavelength assignment separately. To deal with this issue, we propose a reliability-aware joint design method coordinating application mapping and wavelength assignment schemes. For a given application core graph and a network architecture, the design method can obtain a result of application mapping and wavelength assignment with improved reliability, compared to the separate scheme. According to the evaluation of Optical Signal-to-Noise Ratio (OSNR), the proposed method enables more reliable communication under given applications.

MultiSpectralNet: Spectral Clustering Using Deep Neural Network for Multi-View Data

Multi-view data provide more comprehensive information than single views by providing different feature sets of the same object. Learning its data structure through spectral clustering has always been the mainstream of research. However, due to the limitation of its core graph theory, traditional spectral graph-based multi-view clustering algorithms are inapplicable for analyzing large-scale data sets. In this paper, we propose MultiSpectralNet (MvSN), a deep learning approach to spectral multi-view clustering, provides mapping multi-view data points to their fusion eigenvectors and can obtain a more accurate data structure by correcting the misleading information in the single views to a certain extent by feedback in the network training process. In addition, our model can cluster large multi-view data sets and provide cluster prediction for out-of-sample extension. We test ACC and normalized mutual information (NMI) of our method in clustering several artificial and real-world data sets, and the experimental results show that our method outperforms conventional compared state-of-the-art works.

Graph sampling for Internet topologies using normalized Laplacian spectral features

A crucial task in the process of constructing Internet testbeds is to substantially reduce the number of nodes in the interdomain Internet topology, while maintaining its essential properties. In this paper, we first decompose the Internet topology into seven bipartite graphs, a matching graph and a core graph using two normalized Laplacian spectral features, namely, the weighted spectral distribution and the multiplicity of the eigenvalue 1. Then, we accomplish a marked reduction in size of the topology by sampling and merging these graphs. The proposed approach was tested on realistic Internet graphs that were explored from 2000 to 2016 and a large-scale simulated graph. The experimental results confirm that our approach can effectively reduce the number of nodes in these graphs by more than 96%, while maintaining their essential properties.

Incremental Frequent Subgraph Mining on Large Evolving Graphs

Frequent subgraph mining is a core graph operation used in many domains, such as graph data management and knowledge exploration, bioinformatics, and security. Most existing techniques target static graphs. However, modern applications, such as social networks, utilize large evolving graphs. Mining these graphs using existing techniques is infeasible, due to the high computational cost. In this paper, we propose IncGM+ , a fast incremental approach for continuous frequent subgraph mining on a single large evolving graph. We adapt the notion of “fringe” to the graph context, that is the set of subgraphs on the border between frequent and infrequent subgraphs. IncGM+ maintains fringe subgraphs and exploits them to prune the search space. To boost the efficiency, we propose an efficient index structure to maintain selected embeddings with minimal memory overhead. These embeddings are utilized to avoid redundant expensive subgraph isomorphism operations. Moreover, the proposed system supports batch updates. Using large real-world graphs, we experimentally verify that IncGM+ outperforms existing methods by up to three orders of magnitude, scales to much larger graphs and consumes less memory.

Area Constrained Performance Optimized ASNoC Synthesis with Thermal‐aware White Space Allocation and Redistribution

Application-Specific Network-on-Chip (ASNoC) has emerged as a more efficient design alternative to the regular Network-on-Chip (NoC) topologies, which can better suit the communication requirements of an application. In this work, we have proposed a three step ASNoC synthesis procedure that targets optimization of the three major design parameters – area of the chip, communication cost (CC) of the resulting on-chip network and the peak temperature of the chip (Tpeak). Inputs to the procedure are the core dimensions, corresponding average power consumptions and the core graph of the application. In the first step, an area-optimized floorplanning of the cores has been conducted. Considering an overhead constraint on the minimum area generated in this step, a communication cost aware floorplan has been generated in the second step. Finally, considering an overhead constraint on the minimum CC obtained from the second step, a thermal-aware white space allocation and redistribution (WSA&R) has been carried out. At each step, Mixed Integer Linear Programming (MILP) formulation has been made along with heuristic or meta-heuristic methods. Core placement has been performed using a Simulated Annealing (SA) based technique with its initial solution generated using a Particle Swarm Optimization (PSO) based approach. A router placement heuristic has been proposed that considers core rotation and core mirroring techniques to optimally place the primary routers. WSA&R has been performed using an iterative SA-based approach. At each stage of the design flow, we have compared our proposed method with an MILP based method and other contemporary heuristics. Significant improvements have been achieved in both CC and Tpeak. The proposed WSR method has been able to reduce Tpeak up to 22°, considering 35% overhead on CC.

System level fault-tolerance core mapping and FPGA-based verification of NoC

This paper proposes a fault-tolerance network on chip (FTNoC) algorithm that incorporates a core graph unit, which is responsible for mapping and scheduling the core graph on the NoC architecture. Fault tolerance unit collects all the fault information from the mapped NoC platform and provides various solutions for different types of fault. This results in reliable core mapping and improved performance when a fault-related error occurs on an NoC. The proposed FTNoC algorithm was simulated and verified on Kintex-7 (KC705) FPGA board. The results revealed a reduction in area, power consumption and performance improvement compared with previous state-of-the art works.

High-performance and energy-efficient fault-tolerance core mapping in NoC

Network on Chip (NoC) has been proposed as an efficient solution to communication problems in on-chip processors. The probability of failure increases in these systems because the complexity involved in continuous device scaling and the number of components embedded on a chip increases. Therefore, a fault-tolerant design has become a key aspect of designing chips to enhance the system reliability. This paper proposes a system-level mapping technique called FTCM, which enhances the performance and communication energy. It emphasizes on core mapping based on the application core graph and spare core placement in non faulty available processing cores because of core failures in the NoC. This technique mainly focuses on the issue of spare core allocation and its impact on the system performance. Experimental results shows that the communication energy conservation in FTCM is 16.8% compared with FASA and 19.2% compared with FARM, performance improvement of FTCM is 12.6% compared with FASA and 14.77% compared with FARM. Moreover, our method is applicable to both random and distributed core graphs.

Towards Translating Graph Transformation Approaches by Model Transformations

Recently, many researchers are working on semantics preserving model transformation. In the field of graph transformation one can think of translating graph grammars written in one approach to a behaviourally equivalent graph grammar in another approach. In this paper we translate graph grammars developed with the GROOVE tool to AGG graph grammars by first investigating the set of core graph transformation concepts supported by both tools. Then, we define what it means for two graph grammars to be behaviourally equivalent, and for the regarded approaches we actually show how to handle different definitions of both - application conditions and graph structures. The translation itself is explained by means of intuitive examples.

Low Power Low Latency Floorplan‐aware Path Synthesis in Application-Specific Network-on-Chip Design

In Application-Specific Networks-on-Chip (ASNoCs), both positions of the routers and the route for each communication trace of the application can be adjusted to suit the requirements. For an application, input to the current work is a gridded floorplan having fixed positions of cores and routers in it. Maximum physical link length between two routers has been taken as a constraint. For each edge in the application core graph, the proposed method selects a particular path amongst all possible paths, between two grid points. A set of paths is constructed, corresponding to each edge in the core graph, to minimize either the average packet latency or the total router power consumption of the network. The work also inserts junction routers at the intersection of two paths. Secondary routers or repeaters are inserted on a long link, to sustain a pre-specified maximum link length constraint. Alternative paths between routers requiring communication have been generated using a heuristic algorithm. From this, the path synthesis problem has been formulated using a set of linear equations. A Discrete Particle Swarm Optimization (DPSO) based solution has also been proposed for the problem. The path synthesis methodology has been tested with benchmark applications and compared with the shortest path based greedy approaches used by the other ASNoC synthesis methods. The results show a significant improvement in average packet latency and throughput. A power calculator has been developed that computes router power consumption as a function of traffic-load on the router and its number of input and output ports. With the help of the proposed power calculator, a power-aware path synthesis has been accomplished. Synthesized networks have been compared with the networks generated using the shortest path based methods. The proposed method consumes significantly less dynamic power compared to such greedy methods.

A taxonomy for attack graph generation and usage in network security

Attack graphs model possible paths that a potential attacker can use to intrude into a target network. They can be used in determining both proactive and reactive security measures. Attack graph generation is a process that includes vulnerability information processing, collecting network topology and application information, determining reachability conditions among network hosts, and applying the core graph building algorithm. This article introduces a classification scheme for a systematical study of the methods applied in each phase of the attack graph generation process, including the usage of attack graphs for network security. The related works in the literature are stated based on the proposed classification scheme and contributive ideas about potential challenges and open issues for attack graph generation and usage are provided.

Research on solution space of bipartite graph vertex-cover by maximum matchings

.Some algorithms and statistics of the vertex-cover solution space on bipartite graphs are investigated in this paper. Based on ’s theorem, an exact algorithm for solution space expression is proposed and some statistical analysis of the nodes’ states is provided. The statistical results fit well with the algorithmic ones before the emergence of the unfrozen core, which leads to fluctuations of the statistical quantities and produces replica symmetric breaking in the solutions. Besides, the entropy and the clustering entropy of bipartite-graph vertex-cover solutions are calculated using some cycle simplification technique for the unfrozen core. Furthermore, as a generalization of bipartite graphs, a bipartite core graph is proposed, the solution space of which can also be easily determined; and to have further knowledge on the easily-solving vertex-cover instances, how to generate a – subgraph is studied by a growth process of adding edges. The investigation on the solution space of a bipartite-graph vertex-cover provides some insights and intensive understanding on solution space complexity, and will provide benefits in finding the maximum – subgraphs, solving a general-graph vertex-cover and recognizing the intrinsic hardness of NP-complete problems.

A Constructive Heuristic for Application Mapping onto Mesh Based Network-on-Chip

Mapping constitutes a very important step in network-on-chip (NoC)-based implementation of an application. An application is often represented in the form of an application core graph. The cores of the core graph communicate between themselves using the underlying network. This paper presents a constructive heuristic to statically map applications on two-dimensional mesh-connected NoC. The approach corresponds to a design time decision of attachment of cores to the routers. The mapping results, in terms of overall communication cost metric, have been compared with many well-known techniques reported in the literature and also with an exact method built around integer linear programming (ILP). A thorough complexity analysis of the algorithm has been performed. For smaller benchmarks, the results obtained are same as those for the ILP generated solutions. For benchmarks containing 64 and higher number of cores, the mapping solutions are better than the existing ones. Dynamic performances of the mapped solutions have been compared with respect to synthetically generated self-similar traffic. In many cases, our approach requires less latency and energy per packet than the existing methods while providing higher throughput.