CORDIC Method Research Articles

A Scalable Spatial–Temporal Correlated Non-Stationary Channel Fading Generation Method

To address the challenges of complex implementation structures and high hardware resource consumption in multiple-input multiple-output (MIMO) channel emulators, this paper proposes a hardware generation method for spatial–temporal correlated non-stationary channel fading. Firstly, a hardware generation architecture is developed for field-programmable gate array (FPGA) platforms, which can also reduce the complexity of the channel emulator. Secondly, an improved CORDIC method is introduced to reduce algorithm latency and hardware consumption while expanding the function convergence domain, with a relative error maintained at the level of 10-4. Furthermore, based on the idea of time-division multiplexing, an efficient hardware operation of a lower triangular matrix is adopted to minimize the consumption of hardware resources. Finally, the measured results demonstrate that the statistical characteristics of the channel fading generated by the proposed method are in good agreement with the theoretical ones, with an average error of less than 2%. Additionally, under identical simulation conditions, hardware resource consumption is reduced by 6.87%. These findings provide compelling evidence of the enhanced efficiency and accuracy in simulating MIMO channels achieved through the proposed method.

CORDIC-Based General Multiple Fading Generator for Wireless Channel Digital Twin

A wireless channel digital twin is a useful tool to evaluate the performance of a communication system at the physical or link level by generating the physical channel controllably. In this paper, a stochastic general fading channel model is proposed, which considered most of the channel fading types for various communication scenarios. By using the sum-of-frequency-modulation (SoFM) method, the phase discontinuity of the generated channel fading was well addressed. On this basis, a general and flexible generation architecture for channel fading was developed on a field programmable gate array (FPGA) platform. In this architecture, improved CORDIC-based hardware circuits for the trigonometric function, exponential function, and natural logarithm were designed and implemented, which improved the real-time performance of the system and the utilization rate of the hardware resources compared with the traditional LUT and CORDIC method. For a 16-bit fixed-point data bit width single-channel emulation, the hardware resource consumption was significantly reduced from 36.56% to 15.62% for the overall system by utilizing the compact time-division (TD) structure. Moreover, the classical CORDIC method brought an extra latency of 16 system clock cycles, while the latency caused by the improved CORDIC method was decreased by 62.5%. Finally, a generation scheme of a correlated Gaussian sequence was developed to introduce a controllable arbitrary space-time correlation for the channel generator with multiple channels. The output results of the developed generator were consistent with the theoretical results, which verified the correctness of both the generation method and hardware implementation. The proposed channel fading generator can be applied for the emulation of large-scale multiple-input, multiple-output (MIMO) channels under various dynamic communication scenarios.

A Real-Time Hardware Emulator for 3D Non-Stationary U2V Channels

Channel emulator is an important tool to evaluate communication system performance at the physical link, and network levels. In this paper, a new discrete 3D non-stationary geometry-based stochastic model (GBSM) for UAV to vehicle (U2V) channels is proposed, which considers 3D scattering space, 3D trajectory, and 3D antenna array. And a tailed channel emulator is developed on a field programmable gate array (FPGA) platform. All channel parameters, i.e., the power, delay, and phase are calculated by FPGA hardware for the first time instead of software or pre-storage method. Meanwhile, a Greedy CORDIC-based exponential calculation method for generating massive complex sinusoids is designed and implemented. The latency is reduced by 50% than traditional CORDIC method. By further utilizing the compact architecture with time division scheme, the hardware resource is significantly reduced from 16.51% to 7.55% for 16-bit data width. Meanwhile, the fixed-point output statistical properties are also derived for quantitatively validation. Finally, the U2V channel under the campus scenario is reproduced by the proposed emulator. The generated results demonstrate that the statistical properties are consistent well with the theoretical and ray tracing ones, which verifies the correctness of both proposed channel model and emulator.

A Novel Coordinate Rotation Digital Computer Method for Energy and Latency Saving by Trigonometric Operations Spatial Locality Principle

In this work, we propose an approximate and energy-efficient CORDIC method, based on a trigonometric function spatial locality principle derived from benchmarks profiling. Successive sine/cosine computation requests cover more than 50% when the absolute phase difference is at most ten degrees. Consequently, this property suggests an optimized circuit implementation, both iterative or a succession of microrotation modules, where the last CORDIC requires fewer iterations, reducing the latency and the total energy budget at the same precision of two separate and independent instances. Thus, this simple design strategy allows significant area and energy dissipation in general-purpose VLSI architectures, but it introduces also dramatically optimizations in applicationspecific embedded systems used in the area of signal processing and radio frequency communication. In this contribution, we introduce a method, the hardware overhead and the energy budget per single cycle. Simulation results show the total energy saving in considered benchmarks is 40% in pipelined and iterative general purposes CORDIC. Furthermore, our application-specific systems (fast Fourier transform and digital oscillators for radiofrequency down conversions) show remarkable cycle savings when the successive sine/cosine computation requests are more than 70%. Finally, in this work, we extend the proposed approach to whichever phase difference less than 26.56° , as a variable for the second CORDIC number of angle rotations.

A 1-V to 0.29-V sub-100-pJ/operation ultra-low power fast-convergence CORDIC processor in 0.18-μm CMOS

In this paper, an ultra-low power fast-convergence CORDIC processor is proposed for power-constrained applications. Existing fast-convergence CORDIC methods are reviewed. Effective design techniques are proposed to maximize the energy efficiency of the proposed CORDIC processor from algorithm, architecture, to circuit levels. At the algorithm level, an efficient Pipeline Angle Recoding method is proposed to not only significantly reduce the redundant iterations by more than 50%, but also balance the computation load between the optimum angle selection and elementary angle rotation. At the architecture level, efficient pipeline operation is implemented to achieve near 100% hardware utilization and scaling operation during rotations, by scheduling and balancing the pipeline operations between the optimum angle selection unit and the main CORDIC rotation unit with in-rotation scaling logic. The optimum angle selection enable fast-convergence computation and reduce dynamic energy significantly, while the balanced pipeline operation maximize the hardware utilization and also minimize the leakage energy especially at ultra-low voltages in sub/near-threshold regions. Silicon measurement results show that the proposed CORDIC processor fabricated in 0.18-μm CMOS technology can operate from 1 V down to 0.25 V and achieve ultra-low energy consumption at sub-100 pJ when operating in the near/sub-threshold region from 0.57 V to 0.25 V, which is suitable for middle- and low-data rate power-constrained applications. Compared with the conventional design at 1.8 V, the proposed ultra-low voltage CORDIC processor design achieves a 30× reduction in energy consumption and only consumes 35 pJ per CORDIC operating at the minimum energy point of 30 kHz and 0.29 V, making it very suitable for stringently power-constrained applications including wearable healthcare and remote environmental monitoring applications.

Decimal CORDIC Rotation based on Selection by Rounding: Algorithm and Architecture

Hardware implementation of decimal floating-point arithmetic is a topic of great interest among the researchers in computer arithmetic and also the digital processor industry. Software packages for decimal arithmetic are actually being challenged by decimal hardware units. This spreading trend seems to include hardware implementation of elementary functions. The (Coordinate Rotation Digital Computer) CORDIC algorithm, due to its simplicity, is one of the most efficient methods for computing elementary functions. In this work, we develop a decimal CORDIC scheme with almost half number of equally long cycles with respect to the best previous design. This is achieved via retiming of the conventional CORDIC architecture and selection of the microrotation factors by rounding. However, the proposed design does not lead to a predetermined constant scaling factor. The solution that we use is to iteratively compute the logarithm of the scaling factor followed by a decimal exponentiation. The same CORDIC hardware is reused for performing the latter. The proposed CORDIC method requires 2n + 3 cycles for n-digit decimal operands vs. 4n cycles of the previous methods. Evaluations with 16-digit operands based on logical effort analysis conclude that the proposed architecture shows 82% speed advantage, at the cost of 60% more area and 2.5Â KB more ROM.

Low Latency Demodulation for Atomic Force Microscopes, Part II: Efficient Calculation of Magnitude and Phase

AbstractThis paper describes methods for doing high-speed, low latency, coherent demodulation of signals for dynamic or AC mode in Atomic Force Microscopes (AFMs), Abramovitch (2010). These demodulation methods allow the system to extract signal information in as little as one cycle of the fundamental oscillation frequency. By having so little latency, the demodulator minimizes the time delay in the servo loop for an AC mode AFM. This in turn minimizes the negative phase effects of the demodulation allowing for higher speed scanning. Part I, Abramovitch (2011), of the paper describes the mixing and integration portion of the demodulator. This part describes efficient methods for extracting magnitude and phase. In particular, the CORDIC method compared to optimized table lookup operations and a phase-locked loop (PLL) based method. The latter two show a significant decrease in latency, with the PLL based method generating the magnitude and phase with virtually no extra latency and a significant savings in resources.

Function approximation on decimal operands

CORDIC is a well-known method to approximate mathematical functions. It basically works as an iterative algorithm for approximating rotation of a two-dimensional vector using only shift and add operations. The method has been widely applied in the design of digital signal processors and in the computation of typical signal processing functions. It was specifically developed to process data expressed in radix-2. On the other hand, decimal computation has been gaining renewed interest over the last few years, and high performance decimal computation systems are being required on different scopes. In this paper, an improved CORDIC-based method so as to approximate functions on decimal operands is proposed. The algorithm will work with BCD operands, so no conversion to/from radix-2 is needed. An important reduction in the number of iterations in comparison to other CORDIC methods is achieved. The new algorithm is implemented on an FPGA so as to obtain results on delay and hardware resources. The experiments showing the advantages of the new method, with regard to both delay and precision, are described.

An iterative method for improving decimal calculations on computers

Since radix-10 arithmetic has been gaining renewed importance over the last few years, high performance decimal systems and techniques are highly demanded. In this paper, a modification of the CORDIC method for decimal arithmetic is proposed so as to improve calculations. The algorithm works with BCD operands and no conversion to binary is needed. A significant reduction in the number of iterations in comparison to the original decimal CORDIC method is achieved. The experiments showing the advantages of the new method are described. Also, the results with regard to delay obtained by means of an FPGA implementation of the method are shown.

¿Como trabajan las calculadoras?

What happens when you press the sine key on your calculator? How does a calculator quickly produce the values of trigonometric functions? For instance, how does the TI-89 calculate sin 1.0? You might be surprised to know that the calculator does not use series or polynomial approximation, but rather a simple algorithm called the CORDIC method. In fact, the CORDIC method is used for almost all function evaluations (trigonometric, logarithmic, exponential, hyperbolic, inverse functions, etc.), and even multiplication and division. In this paper we will present the main ideas of the CORDIC method along with some elementary examples.

Evaluation of CORDIC Algorithms for FPGA Design

This paper presents a study of the suitability for FPGA design of full custom based CORDIC implementations. Since all these methods are based on redundant arithmetic, the FPGA implementation of the required operators to perform the different CORDIC methods has been evaluated. Efficient mappings on FPGA have been performed leading to the fastest implementations. It is concluded that the redundant arithmetic operators require a 4 to 5 times larger area than the conventional architecture and the speed advantages of the full custom design has been lost. That is due to the longer routing delays caused by the increase of the fan-out and the number of nets. Therefore, the redundant arithmetic based CORDIC methods are not suitable for FPGA implementation, and the conventional two's complement architecture leads to the best performance.

CORDIC: Elementary Function Computation Using Recursive Sequences

recursive sequence could produce all, yes all, of the elementary functions. The CORDIC method (COordinate Rotation DIgital Computer) was developed by Jack Volder [6] in the late 1950s to compute trigonometric function values. It was later recognized that with minor modifications all standard elementary functions could be computed using the same algorithm. Hewlett-Packard, while developing the hand-held

Inverse kinematics computations with modified CORDIC iterations

The paper presents hardware solutions for the computation of inverse kinematics. They are based on an existing pipeline arithmetic processor which employs the CORDIC algorithm. It is shown that a slight modification of the standard CORDIC algorithm enables fast and efficient computation of the joint angles for the inverse kinematics. Due to this modification, the hardware amount and the computation time for the inverse kinematics computations are considerably reduced. The method yields an extended convergence range and a reduced number of iterations in comparison to the original CORDIC design. Another advantage of this method is that it yields an enhanced CORDIC functionality. Finally, a novel architecture for a new kinematic processor based on the modified CORDIC method is presented.

The CORDIC algorithm: new results for fast VLSI implementation

After a brief survey of the CORDIC algorithm, some new results that allow fast and easy signed-digit implementation of CORDIC, without modifying the basic iteration step are given. A slight modification would make it possible to use a carry-save representation of numbers, instead of a signed-digit one. The method, called the branching CORDIC method, consists of performing in parallel two classic CORDIC rotations. It gives a constant normalization factor. An online implementation of the algorithm is proposed with an online delay equal to 5 for the sine and cosine functions. >

Alternative signal processor arithmetic for modified implementation of a normalised adaptive channel equaliser

In adaptive digital signal processing, fast multiplication is one of the most important operations and is implemented as an array multiplier in a standard signal processor. For the realisation of more complex algorithms the CORDIC method has also been proposed but rarely used. A signal processor arithmetic based on a CORDIC and an array-multiplier/accumulator unit is proposed in the paper and an efficient implementation of an adaptive equaliser is given as an example. The concept combines the normalised lattice gradient and the well known LMS algorithm. The advantage of this approach is that the gradient lattice algorithm is less complex than the normalised least-squares lattice algorithm and only slightly slower, yet is still much faster than the gradient transversal LMS algorithm. It is shown that the modified CORDIC algorithm with the proposed arithmetic can reduce the computational complexity. To corroborate this point the computional efficiency and the amount of hardware needed for the proposed implementation are investigated.

Redundant and on-line CORDIC: application to matrix triangularization and SVD

Several modifications to the CORDIC method of computing angles and performing rotations are presented: (1) the use of redundant (carry-free) addition instead of a conventional (carry-propagate) one; (2) a representation of angles in a decomposed form to reduce area and communication bandwidth; (3) the use of on-line addition (left-to-right, digit-serial addition) to replace shifters by delays; and (4) the use of online multiplication, square root, and division to compute scaling factors and perform the scaling operations. The modifications improve the speed and the area of CORDIC implementations. The proposed scheme uses efficiently floating-point representations. The application of the modified CORDIC method to matrix triangularization by Givens' rotations and to the computation of the singular value decomposition (SVD) are discussed. >

Hough transform using Cordic method

The purpose of the letter is to demonstrate the usefulness of the Cordic algorithm for implementation of image processing algorithms in dedicated hardware to achieve near real-time processing speed. The Cordic algorithm will be discussed, and also its application for line and circle detection as well as for arbitrary shapes using Hough transforms.

Modified CORDIC algorithm with reduced iterations

In this contribution we present a modified CORDIC algorithm that offers a considerable latency time reduction and chip area savings when compared with the original CORDIC method. The operations used are adds, shifts, and multiplication or division.

A hardware algorithm for computing sine and cosine using redundant binary representation

AbstractA hardware algorithm for computing sine and cosine using redundant binary representation for internal computations is proposed. This paper considers the computation of sine and cosine of angle tH (0; 4) (rad). Our hardware algorithm is a modification of the CORDIC method, and considers gradual rotation of a point on plane orthogonal coordinates about the origin. Sinecosine are calculated by iteratively computing coordinates of the point. The sequences of numbers representing X‐ and Y‐coordinates of the point rotated and the remaining angle of rotation are expressed by a redundant binary representation, where each digit of number is an element of {‐1, 0, 1}. The direction of rotation at each step is determined based on the upper 3 digits of the remaining angle, and all the internal computations are done in the redundant binary number system. Since parallel addition and subtraction of two numbers by a combinational circuit can be done in a fixed time regardless of the number of digits in the redundant binary number system, the computation for one step can be done in a fixed time. Following this algorithm, n‐bit computation of sine‐cosine by a combinational circuit can be done in the computation time proportional to n and with the number of elements proportional to n2. Since the computation time proportional to at least n log n is required in the existing hardware algorithm based on the CORDIC method, our algorithm is more advantageous as the bit length increases. Moreover, faster computation can be done with about the same number of elements for practical bit lengths.