CoolMOS Devices Research Articles

Avalanche Capabilities of Commercial 1200 V 4H-SiC Power MOSFETs

Avalanche testing is a common method for evaluating the ruggedness of switching devices. Typically, datasheets specify an avalanche rating under a single operating condition. Instead, in this work, 1.2 kV, 24 A SiC MOSFETs are subjected to avalanche events under a variety of conditions. From this testing, a curve is drawn which shows the area for safe avalanche operation. Post-characterization and high temperature reverse bias testing were performed to ensure that the avalanche events did not degrade the device performance or lifetime. CoolMOS devices were also tested for comparison, and, unlike the SiC MOSFETs, the Si devices showed a notable decrease in avalanche capability as the current in avalanche was increased. The SiC MOSFETs were able to endure one hundred single avalanche events at 20 A and 1000 mJ without any sign of lifetime degradation.

Voltage Switching Limits of Lateral GaN Power Devices

The dv/dt switching limitations of power semiconductor devices are evaluated in a boost (PFC) power converter using circuit simulations. State-of-the-art commercial silicon CoolMOS devices, commercial Silicon Carbide (SiC) Junction Barrier Schottky (JBS) diodes, and emerging Gallium Nitride (GaN) lateral power transistors are considered. It is shown that although SiC and GaN power devices have low stored charge and small capacitances, they experience high switching dv/dt stresses which may pose serious switching limitations especially in high-frequency power converters. This problem is likely to be further exacerbated by the presence of a high density of crystal defects in SiC and GaN materials which will manifest in the form of poor field-reliability. Specific guidelines for device selection are recommended in order to optimize both performance and field-reliability.

Imaging Superjunctions in CoolMOS Devices Using Electron Beam Induced Current

Electron beam induced current (EBIC) measurements were used to produce cross sectional images of superjunctions in CoolMOS™ power transistors. The positions of the pn-junctions were determined by EBIC measurements. Knowing the exact locations of the pn-junctions is important for CoolMOS™ since it relies on the principle of charge compensation. For charge compensation, the donors in the n-doped regions must be compensated by an equal amount of acceptors in the p-doped regions. We show that EBIC can provide valuable input for process tuning and process simulations. This will enable the use of smaller dimensions and higher doping levels resulting in a lower on-state resistance.

Experimental Behavior of Single-Chip IGBT and COOLMOS Devices Under Repetitive Short-Circuit Conditions

This work presents the behavior of single-chip insulated gate bipolar transistors (IGBT) devices under repetitive short-circuit operations. The 600 and 1200 V nonpunch through IGBTs as well as 600 V COOLMOS (trademark of Infineon Technologies) have been tested. The repetition of these severe working conditions is responsible for devices ageing, and results unavoidably in the components failure. A series of experimental tests were made in order to determine the number of short-circuit operations the devices can support before failure for different dissipated energies. The temperature influence has been also investigated. Results show two distinct failure modes depending on the dissipated energy during the tests. A critical value of short-circuit energy has been pointed out which separates these failure modes. Experimental and numerical investigations have been carried out in order to analyze these failure modes. A detailed analysis of the physical mechanisms occurring during the short-circuit failures for dissipated energies equal or lightly higher than the critical value is presented.