Conventional Three-level Inverter Research Articles

Current Control of Three-Phase Inverter Using Multiple Bidirectional Choppers Intended for 1.5-kV PV Systems

This article deals with a three-phase inverter for utility-scale photovoltaic (PV) systems where multiple cascaded bidirectional choppers and a three-phase line-frequency transformer with a three-legged core are used. It can achieve a wider maximum-power-point-tracking operating voltage range and the elimination of high-frequency circulating current under the parallel operation of inverters simultaneously. Meanwhile, the conventional current control method based on three-phase <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$d-q-0$</tex-math></inline-formula> transformation suffers from system instability due to a singular point existing in the dc input voltage. For solving this problem, this article proposes a new current control for the three-phase inverter, which is based on the individual current control. The proposed PV inverter structure and the current control method are designed for application in a 1.5-kV megawatt power level PV system. The validity of the control method under active and reactive power control is proved by conducting experiments using a 1.5-kW downscaled model. Furthermore, loss analyses along with comparisons with the conventional three-level inverter are provided.

Novel discontinuous PWM for dc-link voltage balancing of multilevel quasi-nested topologies

ABSTRACT The use of multilevel power converters for its application in high demanding industrial processes and grid connected renewable energy conversion systems has nowadays become the most suitable solution. The main advantages of these converter configurations are: reduction in the blocking voltage stress, lower harmonic ratings, smaller filters for output and input stages. The proposed quasi-nested topology merges the advantages of the classical multilevel topologies, such as the NPC and ANPC configurations, addressing less active switching devices, lower blocking voltage stress. A novel discontinuous modulation technique, with controlled discontinuous gain, is implemented in order to deal with the dc-link voltage unbalance. Simulation and experimental validation results in a scaled-down power 1,5 kW three-phase converter prototype under different operational conditions using different modulation index are presented. The proposed four-level converter topology allows generating an additional output voltage level with the same semiconductor count as conventional three-level inverters such as NPC and ANPC with superior waveform quality, with a THDv reduction of 34.54% in comparison to the clamped inverters. Experimental tests carried out in a 1.5 kW setup verify the feasibility of the proposed topology and the developed discontinuous modulation scheme, to achieve dc-link voltage compensation.

Cascaded Multilevel Inverter-Based Asymmetric Static Synchronous Compensator of Reactive Power

The topology of the static synchronous compensator of reactive power for a low-voltage three-phase utility grid capable of asymmetric reactive power compensation in grid phases has been proposed and analysed. It is implemented using separate, independent cascaded H-bridge multilevel inverters for each phase. Every inverter includes two H-bridge cascades. The first cascade operating at grid frequency is implemented using thyristors, and the second one—operating at high frequency is based on the high-speed MOSFET transistors. The investigation shows that the proposed compensator is able to compensate the reactive power in a low-voltage three-phase grid when phases are loaded by highly asymmetrical reactive loads and provides up to three times lower power losses in the compensator as compared with the situation when the compensator is based on the conventional three-level inverters implemented using IGBT transistors.

Four-Level Quasi-Nested Inverter Topology for Single-Phase Applications

In this paper, a novel four-level single-phase multilevel converter is introduced, consisting of six active switches arranged in a quasi-nested configuration. The proposed topology synthesizes its output voltage levels with respect to a floating neutral point, using four cascaded capacitors with identical voltage levels. The proposed converter contains a reduced number of components compared to the neutral point clamped (NPC) or active-NPC topologies (ANPC) for the same number of output voltage levels, since it does not require diode or active switch clamping to a neutral point. Moreover, no floating capacitors with asymmetric voltage levels are employed, thereby simplifying the capacitor voltage balancing. The switching operation principles, modulation technique and control scheme for supplying a single-phase resistive-inductive load are addressed in detail. The proposed four-level inverter allows generating an additional output voltage level with the same semiconductor count as conventional three-level inverters such as NPC and ANPC which allows a superior waveform quality, with a THDv reduction of 32.69% in comparison the clamped inverters. Experimental tests carried out in a laboratory-scale setup verify the feasibility of the proposed topology.

Leakage Current Suppression of Single-Phase Five-Level Inverter for Transformerless Photovoltaic System

The single-phase five-level transformerless inverters have been gradually applied in photovoltaic grid-connected systems due to low voltage stress and excellent waveform quality. However, they also suffer from serious leakage current as conventional three-level inverters. In order to reduce the leakage current, a single-phase five-level transformerless inverter is proposed in this article. The proposed inverter guarantees that the common-mode (CM) voltage is clamped to a half of the dc-link voltage when outputting ±V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> /2 and zero voltage levels. Consequently, the high-frequency CM voltage is avoided and the leakage current is suppressed. The voltage stresses of eight switches and two flying capacitors are only V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> /4, thus the system investment cost and total losses are reduced. The conduction and switching losses are analyzed in detail and a comparison with some existing topologies is also made. Finally, simulations and experiment are carried out based on a 1-kW prototype. The results show that the proposed single-phase five-level inverter can obtain both excellent differential-mode and CM performance.

Simultaneous Common-Mode Voltage Reduction and Neutral-Point Voltage Balance Scheme for the Quasi-Z-Source Three-Level T-Type Inverter

The conventional three-level inverter only has voltage buck capability. The quasi-Z-source three-level T-type inverter (QZS 3LT $^2$ I) has been proposed to realize voltage buck–boost operation. In this paper, we further propose a novel modulation scheme for the QZS 3LT $^2$ I to realize voltage boosting, reduce the common-mode voltage (CMV), and control the neutral-point voltage balance simultaneously. The proposed scheme adopts a large vector, a medium vector, a small vector with low CMV magnitude, a zero vector, and a shoot-through vector to generate the output voltage. According to sector number and neutral-point voltage difference, a p-type or n-type small vector with low CMV magnitude is properly selected to balance the neutral-point voltage. Shoot-through states are inserted within zero vector to boost the dc input voltage without affecting the ac output voltage. Dwell times of basic vectors are calculated through the revised volt–second balance equation. Furthermore, a coordinate control strategy between neutral-point voltage balance and voltage boosting is proposed. Doing so, the CMV magnitude can be restricted within one-sixth of dc-link voltage and neutral-point voltage imbalance can be effectively mitigated. The effectiveness of the proposed scheme is verified by simulations and experiments.

Direct Torque Control of Low-Voltage Three-Phase Induction Motor Using a Three-Level Eight-Switch Inverter

Speed control of conventional low-voltage low-power induction motors (LV-LP-IMs) by two-level voltage source inverter (2LVSI) has some difficulties due to limitations of LV-LP-IMs especially insulation system. Besides, the use of multilevel inverters is not cost-effective either. In this paper, the new topology of reduced-switch-count three-level inverter with only eight switches is proposed for speed controlling of LV-LP IM. Eight-switch inverter is a newly three-level converter, which has the fewer number of switching devices, lower cost, smaller volume compared with the conventional three-level inverters, while it has sufficient switching vectors to speed control of IMs. In this paper, the structure and switching vectors of the eight-switch inverter are analyzed, and the direct torque control method based on the switching table and voltage balancing of the DC input voltage are presented for the LV-LP-IM speed control. Simulation results, considering different work conditions, are presented in order to validate finally the good performance of the proposed method. Moreover, the obtained results are compared with 2LVSI and conventional three-level inverters in different aspects.

Harmonic Mitigation in Traction Supply Substation Using Cascaded H-Bridge Converter

&lt;span lang="EN-US"&gt;The conventional three-level inverter has been proposed to act as a recuperating converter in Traction Supply Substation. This converter is mainly used to feed back the regenerative braking energy to the grid. However, passive filter is desired to mitigate the current and voltage harmonics. Therefore, this paper investigates the possibility to use a seven-level Cascaded H-Bridge (CHB) converter as the recuperating converter without additional filtering. The proposed converter is modeled with MATLAB/Simulink simulation software. It is then simulated with two potential modulation schemes, namely Phase-Shifted PWM (PS-PWM) and Phase-Disposition PWM (PD-PWM). The quality of AC waveforms produced by these two modulation methods is compared and studied. The results show that PS-PWM technique is preferable for this application as it offered a clean AC current waveform with less than 5% harmonic distortion. However, a twenty-one-level CHB was predicted to comply with the 8% voltage harmonic requirement.&lt;/span&gt;

A Space Vector Modulation Scheme of the Quasi-Z-Source Three-Level T-Type Inverter for Common-Mode Voltage Reduction

The conventional three-level inverter suffers the limitation of voltage buck operation. In order to give both voltage buck and boost operation capability, the quasi-Z-source three-level T-type inverter (3LT <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> I) has been proposed. This paper further proposes a space vector modulation (SVM) scheme for the quasi-Z-source 3LT <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> I to reduce the magnitude and slew rate of common-mode voltage (CMV). By properly selecting the shoot-through phase, the shoot-through states are inserted within zero vector in order not to affect the active states and output voltage. Doing so, the CMV generated by the quasi-Z-source 3LT <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> I is restricted within one-sixth of dc-link voltage, and voltage boosting and CMV reduction can be simultaneously realized. In addition, high dc-link voltage utilization can be maintained. The proposed scheme has been verified in both simulations and experiments. Comparisons are conducted with the conventional SVM method and the phase-shifted sinusoidal PWM method.

DC offset minimisation of three‐phase multilevel inverter configuration under fault and DC link voltage unbalance conditions

In recent days, multilevel inverters are quite popular in the photovoltaic system to improve the power quality. One of the popular multilevel inverters for medium power applications is neutral point clamping inverter. However, with the limited number of switching combinations, energy balancing and fault-tolerant operation is a major issue. The absence of energy balance mechanism may lead to unequal charge and discharge patterns in the batteries used in off-grid applications, which in turn results in the un-equal voltage at the batteries terminals. The difference in voltage between the sources can introduce the DC voltage offset at AC output, which causes serious problems when fed to the transformers or inductive loads like the induction motor. To address this problem, a five-level inverter is proposed which is capable of energy balancing between the two DC sources, minimising the DC voltage offset and able to operate in some fault-tolerant conditions. At the same time, this topology uses less number of switches as compared to conventional three-phase five-level inverters. The proposed topology is developed by combining conventional two-level and three-level inverters. The topology is verified by simulation using Matlab Simulink and tested on a laboratory prototype. The control algorithm for prototype is implemented with the help of Xilinx SPARTAN-6 (XC6SLX9) FPGA board.

Simplified Fault Detection Algorithm for Voltage Source Fed Induction Motor

Industrial applications of induction motor were increased these days due to robust construction. When a three-phase diode clamped inverter is driving this induction motor, the knowledge of inverter performance is very much necessary for the proper operation of induction motor drive. Conventional three-level inverter can drive the induction motor for its speed control. Out of various configurations of MLI, Diode clamped MLI is popular. It has the advantages of simple configuration and requires less number of individual DC sources. But the basic knowledge of faults in the inverter circuit can be very handy for the effective design of induction motor drive system. For the fault mitigation basically the fault detection is to be known. This paper introduces a simple algorithm for the fault identification. This algorithm is very much useful in finding the faulty phase. Out of different faults in the inverter circuit, gate driver faults are common and this paper discusses the gate open fault which is very often fault in the inverter circuit. The simple algorithm also can detect the switch in a leg where this fault occurs. This algorithm is very handy for the fault mitigation. The analysis was carried out using Matlab/Simulink software.

A Fault-Tolerant T-Type Multilevel Inverter Topology With Increased Overload Capability and Soft-Switching Characteristics

The performance of a novel three-phase four-leg fault-tolerant T-type inverter topology is introduced in this paper. This inverter topology provides a fault-tolerant solution to any open-circuit and certain short-circuit switching faults in the power devices. During any of the fault-tolerant operation modes for these device faults, there is no derating required in the inverter output voltage or output power. In addition, overload capability is increased in this new T-type inverter compared to that in the conventional three-level T-type inverter. Such increase in inverter overload capability is due to the utilization of the redundant leg for overload current sharing with other main phase legs under healthy condition. Moreover, if the redundant phase leg is composed of silicon carbide metal-oxide-semiconductor field-effect transistors, quasi-zero-voltage switching, and zero-current switching of the silicon insulated-gate bipolar transistors (IGBTs) in the conventional main phase legs can be achieved at certain switching states, which can significantly relieve the thermal stress on the outer IGBTs and improve the whole inverter efficiency. Simulation and experimental results are given to verify the efficacy and merits of this high-performance fault-tolerant T-type inverter topology.

A Family of Five-Level Dual-Buck Full-Bridge Inverters for Grid-tied Applications

Dual-buck inverters feature some attractive merits, such as no reverse recovery issues of the body diodes and free of shoot-through. However, since the filter inductors of dual-buck inverters operate at each half cycle of the utility grid alternately, the inductor capacity of dual-buck inverters is twice as much as H-bridge inverters. Thus, the power density of dual-buck converters needs to be improved, as well as the conversion efficiency. In this paper, the detailed derivation process of two five-level full-bridge topology generation rules are presented and explained. One is the combination of a conventional three-level full-bridge inverter, a two-level capacitive voltage divider, and a neutral point clamped branch. The other method is to combine a three-level half-bridge inverter and a two-level half-bridge inverter. Furthermore, in order to enhance the reliability of existing five-level DBFBI topologies, an extended five-level DBFBI topology generation method is proposed. The two-level half-bridge inverter is replaced by a two-level dual-buck half-bridge inverter; thus, a family of five-level DBFBI topologies with high reliability is proposed. The operation modes, modulation methods, and control strategies of the series-switch five-level DBFBI topology are analyzed in detail. The power device losses of the three-level DBFBI topology and five-level DBFBI topologies, with different switching frequencies, are calculated and compared. Both the relationship between the neutral point potential self-balancing and the modulation index of inverters are revealed. A universal prototype was built up for the experimental tests of the three-level DBFBI topology, the five-level H-bridge inverter topology, and the existing three five-level DBFBI topologies. Experimental results have shown that the five-level DBFBI topologies exhibit higher efficiency than the five-level H-bridge inverter topology and the three-level DBFBI topology. As well, the higher power density has been achieved by the five-level DBFBI topologies compared with the three-level DBFBI topology.

Two Different Schemes for Three-Level Voltage Space Vector Generation for Induction Motor Drives with Reduced DC-Link Voltage

In this paper, two different schemes for three-level voltage space vector generation for induction motor drives are proposed. In a conventional 3-phase four-pole induction motor, there exist two identical winding coil groups per phase around the stator, which are connected in series and spatially apart by two pole pitches. In this work, these two identical voltage profile pole pair winding coils in each phase of the induction motor are disconnected and reconnected appropriately to achieve a drive scheme with reduced dc-link voltage. Two different schemes are proposed in the present work. In the first scheme the identical pole phase winding groups are connected in two star groups and fed from the independently controlled (decoupled control) two two-level inverters from both sides of the motor with the same dc-link voltage with half the magnitude compared to conventional NPC three-level inverter. The phase windings are connected in two star groups, so there will not be any path for zero sequence currents. Thereby requirement of isolated voltage sources is eliminated compared to the previous open-end winding multilevel inverter schemes. In the second scheme the identical pole phase winding groups are connected in parallel and fed from the two two-level inverters from both sides of the motor with one fourth the dc-link voltage (compared to the conventional NPC three-level inverter) resulting in a three-level voltage space vector across the motor phase windings. The schemes presented in this paper, does not require any special design modification for the induction machine. For the present study, a four pole IM drive is used, and the scheme can be easily extended to induction motors with more than four poles. The proposed scheme is experimentally verified on a four pole, 5HP induction motor drive.

A DC-Link Capacitor Voltage Balancing with CMV Elimination Using Only the Switching State Redundancies for a Reduced Switch Count Multi-Level Inverter Fed IM Drive

Common mode voltage (CMV) variations in PWM inverter-fed drives generate unwanted shaft and bearing current resulting in early motor failure. Multilevel inverters reduce this problem to some extent, with higher number of levels. But the complexity of the power circuit increases with an increase in the number of inverter voltage levels. In this paper a five-level inverter structure is proposed for open-end winding induction motor (IM) drives, by cascading only two conventional two-level and three-level inverters, with the elimination of the common mode voltage over the entire modulation range. The DC link power supply requirement is also optimized by means of DC link capacitor voltage balancing, with PWM control, using only inverter switching state redundancies. The proposed power circuit gives a simple power bus structure.

Three-level inverter scheme with reduced power device count for an induction motor drive with common-mode voltage elimination

A three-level inverter scheme with common-mode voltage elimination and reduced power device count for dual inverter-fed open-end winding induction motor is proposed. The open-end winding induction motor is fed by two three-level inverters, formed by cascading two two-level inverters, from both sides. These two three-level inverters share the top inverter, thereby reducing the power device count. The switching states with zero common-mode voltage variation are selected for pulse-width modulated switching so that there is no alternating common-mode voltage in the pole voltages and phase voltages. Only two DC links, with half the ratings of a conventional three-level neutral point clamped inverter, are used for the proposed scheme.

A Novel NPC Inverter for Harmonics Elimination and Reactive Power Compensation

A three-phase two-leg NPC inverter is presented for power quality compensator. Eight power switches instead of twelve power switches used in the conventional three-level inverter are adopted in the adopted inverter. The voltage stress of power semiconductors is equal to half dc bus voltage instead of full dc bus voltage in the conventional two-level inverter. In this paper, the proposed inverter is operated as a power quality compensator to supply the active power for the dc or ac load and to eliminate harmonics and reactive power drawn from the nonlinear loads. Therefore, the balanced and sinusoidal line currents are drawn from the ac system. To derive the necessary active power and maintain the constant dc bus voltage, a dc bus voltage control in the outer low-bandwidth control system is used. A carrier-based current control in the inner high-bandwidth control system is used to track the line current commands. The mathematical model of the proposed converter is derived and the control algorithm is provided. Simulation and Experiments based on a laboratory prototype are presented to verify the effectiveness of the proposed control scheme.

A Dual Two-Level Inverter Scheme With Common Mode Voltage Elimination for an Induction Motor Drive

Pulse-width modulated (PWM) inverters are known to generate common mode voltages which cause motor bearing currents in the induction motor drives. They also result in leakage currents which act as sources of conducted electromagnetic interference in the drive system. The common mode voltage generated by a conventional three-level inverter can be eliminated by switching only the voltage space vectors which do not produce the common mode voltage. This paper presents a PWM switching strategy to eliminate common mode voltage using the open-end winding configuration for the induction motor. The switching strategy presented in this paper, does not generate any alternating common mode voltages in the drive system and hence the electrostatic coupling of the common mode voltage, which results in the bearing currents and the leakage currents, is avoided. The proposed scheme is devoid of neutral point voltage fluctuations and does not require neutral point clamping diodes, when compared to the common mode elimination scheme based on the conventional three-level inverter topology. Also, the present scheme uses a single dc-link with half the voltage compared to the conventional three-level inverter based scheme.

Dual two-level inverter scheme for an open-end winding induction motor drive with a single DC power supply and improved DC bus utilisation

A dual two-level inverter fed open-end winding induction motor drive with a single DC-power supply is proposed. The proposed scheme produces voltage space vector locations identical to those of a conventional three-level inverter. In the conventional neutral-clamped three-level inverter, the series-connected DC link capacitors carry the load current, resulting in a fluctuating neutral point. Also, a three-level inverter requires bulky DC link capacitors. In the proposed scheme, the DC link capacitors carry currents of higher frequency and hence the neutral point fluctuations are reduced. A PWM switching strategy to suppress the zero sequence currents for all the voltage space phasor combinations is also proposed. This strategy is an improvisation of the one that uses a switched neutral to eliminate the triplen harmonic currents and results in an improved DC bus utilisation.

Three-level space vector PWM in low index modulation region avoiding narrow pulse problem

In using GTO, a few hundreds micro seconds longer than specified pulse width must be guaranteed for safety for each device to commutate with its inherent gate current sequences. This paper describes the mechanism of generating undesirable narrow pulses in conventional three-level space vector PWM inverters and suggests two new algorithms of space vector PWM using nonnearest three and four vectors in a control period to avoid such a narrow pulse problem. Experimental verifications for the suggested algorithms are also presented. >