Conventional Ternary Content Addressable Memory Research Articles

A novel algorithmic Data-Collision SDRAM-based TCAM architecture on FPGA

Ternary Content-Addressable Memory (TCAM) is one of the most effective methods for high-speed data searching in networking infrastructure. Despite the excellent performance and large look-up table, application-specific integrated- circuit-based TCAMs cost massive power supply and are challenging to configure. Field-Programmable Gate Arrays (FPGAs) have become the alternative solution for integrating TCAM due to their minimal power consumption and reconfigurability. Methods using on-chip registers, BRAMs, or LUTRAMs to implement large-size TCAM suffer excessive resource consumption. Researchers introduced DDR-SDRAM-based CAM to provide high-performance and economic packet inspections to overcome such issues; however, they only support binary look-up. This paper presents a novel algorithmic Data-Collision TCAM architecture on FPGA for SDRAM compatibility. The proposed SDRAM- based TCAM supports ternary value look-up function for practical Ethernet packet processing. The architecture outperforms conventional TCAMs regarding BRAMs, logics consumption, and look-up table sizes. The proposed architecture is the first SDRAM-based TCAM on FPGA with a 128Mbyte look-up table.

DyTAN: Dynamic Ternary Content Addressable Memory Using Nanoelectromechanical Relays

Ternary content addressable memory (TCAM) is one type of associative memory and has been widely used in caches, routers, and many other mapping-aware applications. While the conventional SRAM-based TCAM is high speed and bulky, there have been denser but slower and less reliable nonvolatile TCAMs using nonvolatile memory (NVM) devices. Meanwhile, some CMOS TCAMs using dynamic memories have been also proposed. Although dynamic TCAM could be denser than the 16T SRAM TCAM and more reliable than the nonvolatile TCAMs, CMOS dynamic TCAMs still suffer from the row-by-row refresh energy and time overheads. In this article, we propose dynamic TCAM using nanoelectromechanical (NEM) relays (DyTAN), and utilize one-shot refresh (OSR) to solve the memory refresh problem. By exploiting the unique NEM relay characteristics, DyTAN outperforms the existing works in the balance between density, speed, and power efficiency. Compared with the 16T SRAM-based TCAM, the 5T CMOS dynamic TCAM, the 2T2R TCAM, and the 2FeFET TCAM, evaluations show that the proposed DyTAN reduces the write energy by up to $2.3\times $ , $1.3\times $ , $131\times $ , and $13.5\times $ , and improves the search energy-delay-product (EDP) by up to $12.7\times $ , $1.7\times $ , $1.3\times $ , and $2.8\times $ , respectively.

Nanoelectromechanical-Switch-Based Ternary Content-Addressable Memory (NEMTCAM)

A tristate-nanoelectromechanical-switch-based ternary content-addressable memory (NEMTCAM) is proposed for the first time. In the proposed unit NEMTCAM cell, a single nanoelectromechanical (NEM) memory switch replaces two static random access memory cells. Due to the monolithic 3-D (M3D) integration and nonvolatile property of NEM memory switches, the proposed NEMTCAM achieves an 86.3% smaller area, 75.0% lower dynamic power consumption, and a 76.6% higher search speed than conventional ternary content-addressable memory (TCAM) in addition to a negligible static leakage current.

In-Memory Computing with Memristor Content Addressable Memories for Pattern Matching.

The dramatic rise of data-intensive workloads has revived application-specific computational hardware for continuing speed and power improvements, frequently achieved by limiting data movement and implementing "in-memory computation". However, conventional complementary metal oxide semiconductor (CMOS) circuit designs can still suffer low power efficiency, motivating designs leveraging nonvolatile resistive random access memory (ReRAM), and with many studies focusing on crossbar circuit architectures. Another circuit primitive-content addressable memory (CAM)-shows great promise for mapping a diverse range of computational models for in-memory computation, with recent ReRAM-CAM designs proposed but few experimentally demonstrated. Here, programming and control of memristors across an 86 × 12 memristor ternary CAM (TCAM) array integrated with CMOS are demonstrated, and parameter tradeoffs for optimizing speed and search margin are evaluated. In addition to smaller area, this memristor TCAM results in significantly lower power due to very low programmable conductance states, motivating CAM use in a wider range of computational applications than conventional TCAMs are confined to today. Finally, the first experimental demonstration of two computational models in memristor TCAM arrays is reported: regular expression matching in a finite state machine for network security intrusion detection and definable inexact pattern matching in a Levenshtein automata for genomic sequencing.

Energy-Efficient Precharge-Free Ternary Content Addressable Memory (TCAM) for High Search Rate Applications

Hardware search engines (HSEs) have been drawing significant attention in replacing software search algorithms in order to speed up location access and data association in modern systems. Content addressable memory (CAM) is one of the promising HSEs due to its parallel search accessibility. However, it is subjected to considerable dissipation which becomes severe while accessing many components including cells and associated matchlines (MLs) during every search. Ternary CAM (TCAM) based routing tables, especially employed in network systems for packet classification, has put a challenge to design energy-efficient architectures with high-performance and reliable look-up operation. Precharge-free CAM schemes are preferred solutions over precharge types to accomplish high-speed as well as low-power goals of associative memory design. In order to overcome the drawbacks of precharge based designs and also to improve performance during the search, we introduce a precharge-free ternary content addressable memory (PF-TCAM). The proposed searching approach enhances the rate of search by reducing half of the ML evaluation time as it eliminates precharge phase prior to every search by performing search in HALF clock cycle. A $32\times 16$ -bit proposed macro is designed using 45-nm CMOS technology and post-layout simulations at 1 V supply shows 56% and 63% energy efficiency improvements compared to conventional TCAM and compact TCAM respectively over 25 different search keys despite increasing evaluation speed by 50% with an area overhead of 1 transistor/cell over compact TCAM.

Ternary content addressable memory for longest prefix matching based on random access memory on field programmable gate array

Conventional ternary content addressable memory (TCAM) provides access to stored data, which consists of '0', '1' and ‘don't care’, and outputs the matched address. Content lookup in TCAM can be done in a single cycle, which makes it very important in applications such as address lookup and deep-packet inspection. This paper proposes an improved TCAM architecture with fast update functionality. To support longest prefix matching (LPM), LPM logic are needed to the proposed TCAM. The latency of the proposed LPM logic is dependent on the number of matching addresses in address prefix comparison. In order to improve the throughput, parallel LPM logic is added to improve the throughput by 10× compared to the one without. Although with resource overhead, the cost of throughput per bit is less as compared to the one without parallel LPM logic.

Fast Content Updating Algorithm for an SRAM-Based TCAM on FPGA

Static random-access memory (SRAM)-based ternary content-addressable memory (TCAM), an alternative to traditional TCAM, where inclusion of SRAM improves the memory access speed, scalability, cost, and storage density compared to conventional TCAM. In order to confidently use the SRAM-based TCAMs in application, an update module (UM) is essential. The UM replaces the old TCAM contents with fresh contents. This letter proposes a fast update mechanism for an SRAM-based TCAM and implements it on Xilinx Virtex-6 field-programmable gate array. To the best of authors’ knowledge, this is the first ever proposal on content-update-module in an SRAM-based TCAM, which consumes least possible clock cycles to update a TCAM word.

Low-Area TCAM Using A Don’t Care Reduction Scheme

This paper proposes a low-area ternary content-addressable memory using a don’t care reduction (DCR) scheme. In Internet Protocol (IP) address, the prefix bits store “0” or “1,” and the remaining bits store “X” (don’t care). The conventional ternary content-addressable memory (TCAM) needs a 2N-bit memory for an N-bit IP address, because its TCAM cell uses 2-bit memory to store a data bit (“0” or “1”) and a don’t care (“X”) bit. However, the proposed DCR TCAM (DCR-TCAM) needs a ( $N + \log _{2}N$ )-bit memory for an N-bit IP address. It also stores N-bit data, but it encodes N-bit “X”s into a $\log_{2}N$ -bit code, storing the first “X” position. The proposed DCR-TCAM performs the function of “X” in the TCAM from the $\log_{2}N$ -bit code by using additional decoders and bypass transistors. A $256 \times 128$ -bit DCR-TCAM chip was fabricated using a 1.2-V, 65-nm CMOS process. Its area is 0.22 mm2, which is only 72% of the conventional TCAM. It expands an effective memory size by applying the data-relocation TCAM scheme. Its energy/bit/search is 0.41 fJ at a clock frequency of 330 MHz.

Design and measurement of fully digital ternary content addressable memory using ratioless static random access memory cells and hierarchical-AND matching comparator

A 36-bit × 32-entry fully digital ternary content addressable memory (TCAM) using the ratioless static random access memory (RL-SRAM) technology and fully complementary hierarchical-AND matching comparators (HAMCs) was developed. Since its fully complementary and digital operation enables the effect of device variabilities to be avoided, it can operate with a quite low supply voltage. A test chip incorporating a conventional TCAM and a proposed 24-transistor ratioless TCAM (RL-TCAM) cells and HAMCs was developed using a 0.18 µm CMOS process. The minimum operating voltage of 0.25 V of the developed RL-TCAM, which is less than half of that of the conventional TCAM, was measured via the conventional CMOS push–pull output buffers with the level-shifting and flipping technique using optimized pull-up voltage and resistors.

Design and Analysis of STTRAM-Based Ternary Content Addressable Memory Cell

Content Addressable Memory (CAM) is widely used in applications where searching a specific pattern of data is a major operation. Conventional CAMs suffer from area, power, and speed limitations. We propose Spin-Torque Transfer RAM--based Ternary CAM (TCAM) cells. The proposed NOR-type TCAM cell has a 62.5% (33%) reduction in number of transistor compared to conventional CMOS TCAMs (spintronic TCAMs). We analyzed the sense margin of the proposed TCAM with respect to 16-, 32-, 64-, 128-, and 256-bit word sizes in 22nm predictive technology. Simulations indicated a reliable sense margin of 50mV even at 0.7V supply voltage for 256-bits word. We also explored a selective threshold voltage modulation of transistors to improve the sense margin and tolerate process and voltage variations. The worst-case search latency and sense margin of 256-bit TCAM is found to be 263ps and 220mV, respectively, at 1V supply voltage. The average search power consumed is 13mW, and the search energy is 4.7fJ/bit search. The write time is 4ns, and the write energy is 0.69pJ/bit. We leverage the NOR-type TCAM design to realize a 9T-2 Magnetic Tunnel Junctions NAND-type TCAM cell that has 43.75% less number of transistors than the conventional CMOS TCAM cell. A NAND-type cell can support up to 64-bit words with a maximum sense margin of up to 33mV. We compare the performance metrics of NOR- and NAND-type TCAM cells with other TCAMs in the literature.

Resource-Efficient SRAM-Based Ternary Content Addressable Memory

Static random access memory (SRAM)-based ternary content addressable memory (TCAM) offers TCAM functionality by emulating it with SRAM. However, this emulation suffers from reduced memory efficiency while mapping the TCAM table on SRAM units. This is due to the limited capacity of the physical addresses in the SRAM unit. This brief offers a novel memory architecture called a resource-efficient SRAM-based TCAM (REST), which emulates TCAM functionality using optimal resources. The SRAM unit is divided into multiple virtual blocks to store the address information presented in the TCAM table. This approach virtually increases the overall address space of the SRAM unit, mapping a greater portion of the TCAM table in SRAM and increasing the overall emulated TCAM bits/SRAM at the cost of reduced throughput. A 72 × 28-bit REST consumes only one 36-kbit SRAM and a few distributed RAMs via implementation on a Xilinx Kintex-7 field-programmable gate array. It uses only 3.5% of the memory resources compared with a conventional SRAM-based TCAM (hybrid-partitioned TCAM).

Low-Power Effective Memory-Size Expanded TCAM Using Data-Relocation Scheme

This paper proposes a low-power effective memory-size expanded ternary content addressable memory (TCAM). The IP address of IPv6 extends to 128 bits, where the prefix bits store `0' or `1' and the remaining bits store `X' (don't care). Most prefixes are much shorter than 128 bits, so many TCAM cells store `X'. The proposed data-relocation TCAM (DR-TCAM) increases the number of IP addresses stored in the TCAM by relocating the data in the prefix bits into `X' cells. The DR-TCAM has four types of banks. The type-0 bank is empty and inactivated. The type-1 and type-2 banks store four 32 bit words and two 64 bit words instead of a 128 bit word in the type-3 bank, respectively. Therefore, the type-1 and type-2 banks store four and two times larger IP addresses, respectively. In the simulation, the area and power consumption of the DR-TCAM decreased to 34% and 36% of those of the conventional TCAM for 4 K IP addresses, respectively. The DR-TCAM chip with 256 × 128 bit TCAM cells and 8 banks was fabricated using a 1.2 V 0.13 μm CMOS process. Its area was 0.87 mm 2 . Its energy/bit/search was 1.3 fJ at 200 MHz clock frequency when 4 banks were activated to store 256 IP addresses.

A Low-Power Ternary Content Addressable Memory With Pai-Sigma Matchlines

This paper proposes a Pai-Sigma matchline scheme to reduce the compare (search) power of a ternary content addressable memory (TCAM). The proposed matchline does not incur the issues of charge sharing and short circuit current, which typically exist in the hybrid nand-nor matchline. Moreover, the switching activity of the search lines of a TCAM with the proposed matchlines is low. A 32×64-bit TCAM with the Pai-Sigma matchlines is implemented to demonstrate the low-power feature. Results show that the compare power of the TCAM can achieve 60% energy reduction compared with the conventional nor-type TCAM. Also, the energy consumption per bit per search of the TCAM is only 2.287 fJ/bit/search.

Design of a 270ps-access 7-transistor/2-magnetic-tunnel-junction cell circuit for a high-speed-search nonvolatile ternary content-addressable memory

A novel 7-transistor/2-magnetic-tunnel-junction (7 T-2MTJ) cell circuit is proposed for a high-speed and compact nonvolatile ternary content-addressable memory (TCAM). Since critical path for switching in the TCAM cell circuit, which determines the performance of the TCAM, is only a single MOS transistor, switching delay of the TCAM word circuit is minimized. As a result, 270 ps of switching delay in 144-bit TCAM word circuit is achieved under a 90 nm CMOS/MTJ technology with magneto-resistance ratio of 100%, which is about two times faster than a conventional CMOS-based TCAM.

Design of a Nine-Transistor/Two-Magnetic-Tunnel-Junction-Cell-Based Low-Energy Nonvolatile Ternary Content-Addressable Memory

Towards a low search-energy nonvolatile ternary content-addressable memory (TCAM), we propose a novel nine-transistor/two-magnetic-tunnel-junction (9T–2MTJ) nonvolatile TCAM cell circuit with a high-speed accessibility. Since critical path for switching in the TCAM cell circuit is only a single metal-oxide-semiconductor (MOS) transistor, switching delay of the TCAM word circuit is minimized. As a result, the worst-case switching delay of 0.22 ns is achieved in a 144-bit word circuit under a 90 nm complementary MOS (CMOS)/MTJ technology, which is about 2.6 times faster than that of a conventional CMOS-based TCAM. In order to minimize the active power dissipation in the proposed TCAM, a multi-level segmented match-line scheme that maximally brings inessential cells to standby state is also applied to the 9T–2MTJ-cell-based word circuit. Finally, low search-energy of 0.73 fJ/bit/search is achieved in a 144-bit × 256-word nonvolatile TCAM together with eliminating standby power using nonvolatility.