Conventional Software Implementation Research Articles

An enhanced implementation of SRF and DDSRF-PLL for three-phase converters in weak grid

Abstract Renewable energy generation systems connected to utility grid require perfect synchronization to grid which is one of the most important issues that needs to be taken into consideration. This paper proposed a hardware-accelerated implementation for the decoupled double synchronous reference frame phase-locked loop (DDSFR-PLL) for grid synchronization in grid-connected converters in weak grid that suffers from phase voltage-unbalance, variable phase and frequency conditions. Since the transformations and filtering of this method is computationally intensive and needs to be executed as fast as possible by the microcontroller unit (MCU) and Due to the presence of other current and voltage regulation loops in the same interrupt service routine (ISR) with high frequency rate, a hardware-based acceleration using the STM32G4x4 MCU built-in filter, filter math accelerator (FMAC) and coordinate rotation digital computer (CORDIC) is used to speed the execution time. This study addresses the description, derivation and implementation of the both DQ-PLL and DDSRF-PLL algorithms. The performance of both pure-software and accelerated implementation is demonstrated, compared and run on a three-level active neutral point clamped (ANPC) converter board. In proposed method, CPU load dropped from 80.5% by using the conventional software implementation to 23.6% (70% load reduction).This reduction in CPU load enables the addition of more features and more advanced current and voltage control algorithms.

Accelerating Intercommunication in Highly Parallel Systems

Every HPC system consists of numerous processing nodes interconnect using a number of different inter-process communication protocols such as Messaging Passing Interface (MPI) and Global Arrays (GA). Traditionally, research has focused on optimizing these protocols and identifying the most suitable ones for each system and/or application. Recently, there has been a proposal to unify the primitive operations of the different inter-processor communication protocols through the Portals library. Portals offer a set of low-level communication routines which can be composed in order to implement the functionality of different intercommunication protocols. However, Portals modularity comes at a performance cost, since it adds one more layer in the actual protocol implementation. This work aims at closing the performance gap between a generic and reusable intercommunication layer, such as Portals, and the several monolithic and highly optimized intercommunication protocols. This is achieved through the development of a novel hardware offload engine efficiently implementing the basic Portals’ modules. Our innovative system is up to two2 orders of magnitude faster than the conventional software implementation of Portals’ while the speedup achieved over the conventional monolithic software implementations of MPI and GAs is more than an order of magnitude. The power consumption of our hardware system is less than 1/100th of what a low-power CPU consumes when executing the Portal's software while its silicon cost is less than 1/10th of that of a very simple RISC CPU. Moreover, our design process is also innovative since we have first modeled the hardware within an untimed virtual prototype which allowed for rapid design space exploration; then we applied a novel methodology to transform the untimed description into an efficient timed hardware description, which was then transformed into a hardware netlist through a High-Level Synthesis (HLS) tool.

A Reconfigurable Architecture for the Detection of Strongly Connected Components

The Strongly Connected Components (SCCs) detection algorithm serves as a keystone for many graph analysis applications. The SCC execution time for large-scale graphs, as with many other graph algorithms, is dominated by memory latency. In this article, we investigate the design of a parallel hardware architecture for the detection of SCCs in directed graphs. We propose a design methodology that alleviates memory latency and problems with irregular memory access. The design is composed of 16 processing elements dedicated to parallel Breadth-First Search (BFS) and eight processing elements dedicated to finding intersection in parallel. Processing elements are organized to reuse resources and utilize memory bandwidth efficiently. We demonstrate a prototype of our design using the Convey HC-2 system, a commercial high-performance reconfigurable computing coprocessor. Our experimental results show a speedup of as much as 17× for detecting SCCs in large-scale graphs when compared to a conventional sequential software implementation.

Hardware Architecture for Video Authentication Using Sensor Pattern Noise

Digital camera identification can be accomplished based on sensor pattern noise, which is unique to a device, and serves as a distinct identification fingerprint. Camera identification and authentication have formed the basis of image/video forensics in legal proceedings. Unfortunately, real-time video source identification is a computationally heavy task, and does not scale well to conventional software implementations on typical embedded devices. In this paper, we propose a hardware architecture for source identification in networked cameras. The underlying algorithms, an orthogonal forward and inverse discrete wavelet transform and minimum mean square error-based estimation, have been optimized for 2-D frame sequences in terms of area and throughput performance. We exploit parallelism, pipelining, and hardware reuse techniques to minimize hardware resource utilization and increase the achievable throughput of the design. A prototype implementation on a Xilinx Virtex-6 FPGA device was optimized with a resulting throughput of 167 MB/s, processing 30 640 × 480 video frames in 0.17 s.

A methodology for speeding up edge and line detection algorithms focusing on memory architecture utilization

In this paper, a new methodology for speeding up edge and line detection algorithms is presented, achieving improved performance over the state of the art software library OpenCV (speedup from 1.35 up to 2.22) and other conventional implementations, in both general and embedded processors, by reducing the number of load/store and arithmetic instructions, the number of data cache accesses and data cache misses in memory hierarchy and the algorithm memory size. This is achieved by fully exploiting the combination of the software and hardware parameters which are considered simultaneously as one problem and not separately. Furthermore, the edge and line detection algorithms have been simplified for a computer vision application in a Virtex-5 Xilinx FPGA using Microblaze soft processor (detection and measurement of flow fronts in a microfluid device); it achieves speedup up to 660 times in comparison with conventional software implementations.

A Methodology for Speeding up MVM for Regular, Toeplitz and Bisymmetric Toeplitz Matrices

The Matrix Vector Multiplication algorithm is an important kernel in most varied domains and application areas and the performance of its implementations highly depends on the memory utilization and data locality. In this paper, a new methodology for MVM including different types of matrices, i.e. Regular, Toeplitz and Bisymmetric Toeplitz, is presented in detail. This methodology achieves higher execution speed than the software state of the art library, ATLAS (speedup from 1.2 up to 4.4), and other conventional software implementations, for both general (SIMD unit is used) and embedded processors. This is achieved by fully and simultaneously exploiting the combination of software and hardware parameters as one problem and not separately.

Design of an efficient communication infrastructure for highly contended locks in many-core CMPs

Lock synchronization is a key programming primitive for shared-memory many-core CMPs. However, as the number of cores increases, conventional software implementations cannot meet the desirable levels of performance and scalability. Meanwhile, most existing hardware-supported lock proposals require modifications at some level of the memory hierarchy, thus degrading QoS of applications through synchronization traffic.In this paper, we propose GLock, a dedicated network infrastructure and a token-based message-passing protocol to provide a non-intrusive, extremely efficient and fair implementation for highly contended locks. Two implementations of GLock are considered. The first leverages current full-custom G-lines technology, whilst the second uses a cost-effective mainstream industrial toolflow with an advanced 45 nm technology. When compared with the most efficient software-based lock, both alternatives provide significant reductions in execution time, network traffic and power consumption, for a representative set of benchmarks, with negligible area overhead.

High-performance hardware implementation of a parallel database search engine for real-time peptide mass fingerprinting

Peptide mass fingerprinting (PMF) is a method for protein identification in which a protein is fragmented by a defined cleavage protocol (usually proteolysis with trypsin), and the masses of these products constitute a 'fingerprint' that can be searched against theoretical fingerprints of all known proteins. In the first stage of PMF, the raw mass spectrometric data are processed to generate a peptide mass list. In the second stage this protein fingerprint is used to search a database of known proteins for the best protein match. Although current software solutions can typically deliver a match in a relatively short time, a system that can find a match in real time could change the way in which PMF is deployed and presented. In a paper published earlier we presented a hardware design of a raw mass spectra processor that, when implemented in Field Programmable Gate Array (FPGA) hardware, achieves almost 170-fold speed gain relative to a conventional software implementation running on a dual processor server. In this article we present a complementary hardware realization of a parallel database search engine that, when running on a Xilinx Virtex 2 FPGA at 100 MHz, delivers 1800-fold speed-up compared with an equivalent C software routine, running on a 3.06 GHz Xeon workstation. The inherent scalability of the design means that processing speed can be multiplied by deploying the design on multiple FPGAs. The database search processor and the mass spectra processor, running on a reconfigurable computing platform, provide a complete real-time PMF protein identification solution.

A hardware Memetic accelerator for VLSI circuit partitioning

During the last decade, the complexity and size of circuits have been rapidly increasing, placing a stressing demand on industry for faster and more efficient CAD tools for VLSI circuit layout. One major problem is the computational requirements for optimizing the place and route operations of a VLSI circuit. Thus, this paper investigates the feasibility of using reconfigurable computing platforms to improve the performance of CAD optimization algorithms for the VLSI circuit partitioning problem. The proposed Genetic algorithm architecture achieves up-to 5× speedup over conventional software implementation while maintaining on average 88% solution quality. Furthermore, a reconfigurable computing based Hybrid Memetic algorithm improves upon this solution while using a fraction of the execution time required by the conventional software based approach.

Genetic algorithm driven hardware–software partitioning for dynamically reconfigurable embedded systems

The need for inexpensive, compact and adaptive systems prompted considerable interest in the hardware–software co-design of embedded systems. In particular, Dynamically Reconfigurable Embedded Systems, which exploit the advances in Field Programmable Gate Array (FPGA) technology, facilitate customisation of their hardware resources during runtime to meet the demands of executing applications. The ability to estimate the resultant acceleration obtained is highly desirable, as time to market deadlines are being ever shortened. The performance of such systems is fundamentally dependent on the hardware–software partition. In this paper, a genetic algorithm-based (GA) hardware–software partitioning method is presented. Demonstrative applications are used to illustrate the effectiveness of the GA approach at exploiting the inherent reconfigurable nature of such systems to obtain optimal or near optimal performance speedup relative to a conventional software implementation.

Improving applications performance

This paper presents a memory model and architecture for synchronization of threads or tasks when accessing regions of virtual memory. Access control is defined on a memory region through a view that defines the size of access units and also the protocol in terms of a Finite State Machine (FSM). The size of access units, although fixed within a view, can vary across views and is thus customizable to applications. Variable-sized access units are obtained without altering the underlying fixed sized paging implementation. By defining access control through FSM definitions, any protocol that is decomposable into a set of states and can be expressed using an FSM can be supported.A cache-based architecture of the Protection Control Unit (PCU), which decides whether a read/write memory access to an access unit of a region/view can proceed or leads to a fault, is presented. The PCU is not invoked on each read/write memory access, but only on data cache misses and write access faults. The cache-based architecture forms flexible hardware support for access control in that by loading the caches with definitions of different FSM, different protocols can be supported. Furthermore, by providing for hardware supported changes in state of access through state transitions, frequency of context switching is reduced.Trace-driven simulation is used to examine the delay in the memory hierarchy due to inclusion of the caches in the PCU unit, and to examine delay in the memory hierarchy for a conventional software implementation of the same access control protocol. A TPC-C benchmark application under different transaction loads was traced and the results show that it is the number of TLB accesses (approximately 15 times more as compared to PCU accesses) for the modeled application that incurs the dominant delay, as compared to delay in the PCU memory hierarchy.

Many-particle interaction problems computed by special purpose processors, with emphasis on the Ising model

The first part of the article describes the power of special purpose computing registers in solving many-particle interaction problems. Dedicated logic and analog circuits are used in combination with general purpose digital computers to implement specific algorithms in hardware. A significant increase in computational speed can thus be obtained. An example is the fast generation of random numbers for Monte Carlo experiments. Hybrid external processors are able to deliver up to 10 7 truly random numbers per second. The prospects for these hybrid techniques in computational physics are discussed. Modern semi-automatic design techniques with the availability of medium scale integrated components allow a competitive design time for the hardware construction compared to the conventional software implementation. In the second part of the article results are described for a 100 x 100 Ising model, calculated with the algorithm of Yang. Also a model of the growth of crystals in a saturated solution is numerically evaluated by a hardware implementation of a special algorithm.

An Innovation in Control Panels for Large Computer Control Systems

A control panel of novel design has been developed at SLAC. This panel, called a touch panel, consists of a glass plate placed in front of a computer driven cathode ray tube display. Ultrasonic surface (Rayleigh) wave (8.5 MHz) beams are transmitted in a crossing X-Y grid through the glass. The intersection points of the beams form the "buttons" on the panel. The computer furnishes legends for these buttons. The presence of an operator's finger on the glass "pushing" a button is detected by the absorption of an X and a Y beam. A prototype panel has been built and used successfully with an SDS-925 computer for magnet control in the SLAC beam switchyard. A second generation panel with low parallax using the glass face of the CRT itself as the medium for ultrasonic propagation has been designed and is being constructed. An extensive software system, utilizing numerous "software panels", for general control of the accelerator, the beam switchyard, and their associated subsystems is being developed. The physical principles of the device, its advantages and disadvantages over conventional devices, current hardware and software implementation, and future plans are discussed.