Conventional Pulse Width Modulation Method Research Articles

Performance Characteristics of a Newly Developed Asymmetric Seven-Level Inverter Utilizing Various Hybrid Pulse Width Modulation Strategies

This study unveils a notable breakthrough in inverter technology, holding promise for substantial improvements in voltage quality and the attenuation of harmonic distortions within power systems. This study concentrates on the design and implementation of a novel Seven-Level Asymmetric Inverter (NSLAI) by incorporating various hybrid Pulse Width Modulation (PWM) techniques. The primary goal is to improve the output voltage magnitude while decreasing the Total harmonics compared to conventional PWM methods. The investigation introduces a novel Seven-Level Asymmetric Inverter (NSLAI) with innovative Hybrid Pulse Width Modulation (PWM) strategy. The purpose of this study is to investigate the distinct features of a recently developed asymmetric seven-level inverter, with a focus on exploring its characteristics through the implementation of diverse hybrid pulse width modulation strategies. Hybrid PWM methodology intricately centers on enhancing voltage quality and achieving better harmonious spectral characteristics. The gate signal producing approach for this suggested PWM technology incorporates a hybrid PWM methodology that combines trapezoidal and sinusoidal waveforms, as well as a standard triangular carrier signal enabling NSLAI. The hybrid version of PWM practices is deliberately used to generate switching signals for the NSLAI. An intensive evaluation of numerous indicators of effectiveness across multiple modulation indexes leads in the demonstrating of quantitative findings that compare the unique Hybrid PWM practice with established PWM tactics. Notably, the hybrid reference Carrier Overlapping strategy has emerged as a leading approach surpassing conventional pulse width modulation techniques. It achieves a significantly higher fundamental Root Mean Square voltage output and remarkably lower percentage of Total Harmonic Distortion values compared to all within the hybrid reference Variable Frequency strategy. The principal analytical tool used in the modeling investigation is MATLAB-SIMULINK. This study marks a watershed moment in the development of inverters, claiming significant improvements in battery power quality and distortion caused by harmonics avoidance across power systems, as evidenced by extensive simulation and prototype-based discoveries.

A hybrid reference pulse width modulation technique for binary source multilevel inverter

The article presents a seven-level reduced switch asymmetrical multilevel inverter with two different methods of pulse width modulation (PWM) techniques. Phase disposition (PD) PWM and hybrid variable-frequency phase disposition PWM (HVFPD-PWM) are the two different PWM methods for making the quality of output voltage waveform. In the first method, the unipolar sine reference with triangular carriers is used. In the second method, the hybrid unipolar reference (sinusoidal with trapezoidal) is proposed with variable frequency carriers to generate the switching pulses for asymmetric multilevel inverter (MLI). The main objective of this proposed method is to reduce the total harmonic distortion in the output voltage waveforms. A comprehensive comparison of the proposed HVFPD-PWM and the conventional PD-PWM with asymmetrical seven-level inverter is presented to show the enriched performances of the proposed method. The performance and viability of the suggested PWM are evaluated through simulation and experimental results using an asymmetrical seven-level inverter. The total harmonic distortion for the proposed PWM method (16.95%) is significantly reduced as compared with the conventional PWM method (18.01%) at the modulation index of one.

A Novel Zero Dead-Time PWM Method to Improve the Current Distortion of a Three-Level NPC Inverter

This paper proposes a novel pulse width modulation (PWM) for a three-level neutral point clamped (NPC) voltage source inverter (VSI). When the conventional PWM method is used in three-level NPC VSI, dead time is required to prevent a short circuit caused by the operation of complementary devices on the upper and lower arms. However, current distortion is increased because of the dead time and it can also cause a voltage unbalance in the dc-link. To solve this problem, we propose a zero dead-time width modulation (ZDPWM) which does not require dead time used in complementary operation. The proposed technique applies the offset voltage to the space vector pulse width modulation (SVPWM) reference voltage for the same modulation index (MI) as the conventional SVPWM, but any complementary switching operation needs dead time. In addition, the proposed method is divided into four operation sections using the reference voltage and phase current to operate switching devices which flow the current depending on the section. This ZDPWM method is simply implemented by carrier and reference voltage that reduce the current distortion, because complementary operation that needs dead time is not implemented. However, the operation section is delayed due to the sampling delay that occurs during the experiment. Therefore, in this paper, we conduct a modeling of sampling delay to improve the delay of operation section. To verify the principle and feasibility of the proposed ZDPWM method, a simulation and experiment are implemented.

SVM Strategy for Mitigating Low-Order Harmonics in Isolated AC–DC Matrix Converter

Isolated ac–dc matrix converter features bidirectional power conversion, galvanic isolation, and high power density. However, the conventional pulsewidth modulation methods in the literature can lead to the input ac distortions in the isolated ac–dc matrix converter with excessive low-order harmonics. To improve the current quality and maintain a low number of switching actions, an improved space vector modulation (SVM) strategy is proposed in this article. The SVM switching sequence and the distribution of zero vectors are designed to mitigate the low-order harmonics. To verify the performance, an in-depth study of the harmonics generation mechanism in the converter is conducted based on a developed mathematical converter model. The performances of the conventional SVM strategy and the proposed SVM strategy are compared, and simulation and experimental results are provided.

Comprehensive Analysis and Experimental Validation of 240$^\circ$-Clamped Space Vector PWM Technique Eliminating Zero States for EV Traction Inverters With Dynamic DC Link

A bus-clamping space vector pulsewidth modulation (PWM) called 240 $^\circ$ -clamped PWM (240CPWM) is analyzed for three-phase converters that have a cascaded connection of a dc–dc stage and a dc–ac stage. A direct application of the proposed concept is electric vehicle (EV) traction inverters that employ a dc–dc stage to interface a relatively low-voltage battery to a high-voltage motor. The 240CPWM method has the major advantages of clamping a phase to the positive or negative rail for 240 $^\circ$ in a fundamental period, clamping of two phases simultaneously at any given instant, and use of only active states, completely eliminating the use of zero states. These characteristics lead to more than seven times reduction in switching losses of the inverter at unity power factor compared to CSVPWM, comparable or better total harmonic distortion (THD) performance, significant reduction in common-mode voltage and high efficiency. The THD of the line current is analyzed using the notion of stator flux ripple and compared with conventional and discontinuous PWM methods. The switching loss characteristics under different power factor conditions are discussed. Experimental results from a 10-kW hardware prototype are presented. The full load efficiency with the proposed 240CPWM for the dc–ac stage exceeds 99% even with Si insulated-gate bipolar transistors (IGBTs).

Analysis of Current Flowing Through Disabled Converters in Parallel AC/DC Power Conversion System

When not all the converters are enabled in a parallel ac/dc power conversion system, some current flows through the disabled converters. This current not only distorts the current waveform of the ac side but also causes extra loss and unintended power flow from the ac to the dc side. In this article, the reason for this current flow is identified, and the total current according to the number of paralleled converters and its operating conditions are analyzed. A new pulsewidth modulation (PWM) method is proposed to minimize the current. And, the zero-sequence voltage and the consequent current flowing through the disabled converters under the proposed PWM method are compared to those under the conventional PWM methods. As a result, it was identified that discontinuous space vector PWM (DPWM) is not a proper PWM method because it causes a large current at some operating conditions. According to both simulation and experimental results, the magnitude of the current flows through disabled converters under the proposed PWM was about 40% less than that under sine PWM and DPWM, and it was about 10% less than that under continuous space vector PWM.

Common mode voltage suppression in three‐phase voltage source inverters with dynamic load

This study proposes a novel pulse width modulation (PWM) algorithm to mitigate the common mode voltage (CMV) in a multi-level voltage source inverter feeding an electric machine. Dead-time effect frequently prevents the CMV not to reach zero in several switching periods. Then the electromagnetic interference noise is generated and causes bearing failure and overvoltage stress on winding insulations. The proposed strategy compensates the dead-time effect that alleviates the high-amplitude rectangular pulses with extreme range of variations during high-frequency switching transitions. The existing PWM methods reduce the CMV to ±V dc /6, however by utilising the presented approach, CMV can be reduced to zero. However, the total harmonic distortion will be increased 0.3% at fundamental current harmonic rather than conventional state PWM method, which could be neglected. Simulation results and efficiency analysis imply on worthy performance of the proposed strategy to eliminate the CMV.

Clamping Angle Control PWM Method to Restore Linear Modulation Range of a Voltage Source Inverter

This paper proposes the new clamping angle control (CAC) pulse width modulation (PWM) method to restore its maximum linear modulation range of voltage source inverters (VSIs) reduced by the duty ratio limitation in hardware implementation, which makes the VSIs to operate nonlinearly in the high modulation range. The deadtime and the bootstrap gate driver circuit mainly cause this duty ratio limitation in practice. In particular, the bootstrap gate driver circuit is used in many industrial applications by avoiding the additional power supply to apply the gate-source voltage of power switches, and therefore making the VSIs to be small size with the low cost. First, the proposed CACPWM method is theoretically analyzed. Then, it is applied in the high modulation range to overcome the limitation of the duty ratio due to the use of the bootstrap gate driver circuit. Thereafter, its practical effectiveness is verified by both simulation and experimental tests. Also, the resulting harmonic distortions are compared with those by the conventional PWM methods.

Finite control set predictive control of shunt hybrid power filter

ABSTRACTThis paper proposes a finite control set predictive control (FCS-PC) scheme for the shunt hybrid power filter (SHPF) to reduce the power loss while maintaining satisfactory power quality at the utility’s grid terminals. By means of the instantaneous power theory, the controller for the proposed method can generate the reference voltage for the SHPF voltage source inverter (VSI) for the future sampling time. Therefore, during a sampling time, the vector of the reference voltage is compared with the finite number of voltage vectors existent in the VSI to select the vector that best fits the cost function of the controller. The proposed method, compared with the conventional pulse width modulation (PWM) carrier method, has the capability of suppressing similarly the harmonic currents at grid terminals and controlling VSI DC-link voltage while maintaining low switching frequencies in the devices. This method shows simplicity in digital implementation because it does not need a PWM block to obtain the VSI gating signals. In addition, a comparison of the proposed FCS-PC method with the conventional carrier-based PWM method is presented and discussed. Parameter errors in the controller are studied and their effects on system performance are explained. The effectiveness of the proposed method is demonstrated with simulation and experimental results during steady-state operation and transient response of the system.

Experimental Comparison of Conventional and Bus-Clamping PWM Methods Based on Electrical and Acoustic Noise Spectra of Induction Motor Drives

The acoustic noise emitted by an induction motor powered by a voltage source inverter (VSI) is an environmental issue. Harmonics present in the stator current are the main reason for the increased acoustic noise in motor drives. The pulse-width modulation (PWM) technique used to modulate the inverter is a key factor in determining the magnitude of current harmonics. Bus-clamping PWM (BCPWM) techniques have got much attention nowadays due to reduced switching loss, compared with conventional space vector PWM (CSVPWM). In this paper, two BCPWM techniques, namely $60^\circ$ and $30^\circ$ BCPWM methods are compared with CSVPWM on the basis of electrical spectra as well as acoustic noise spectra. Experiments are conducted on a pulse-width-modulated VSI-fed induction motor drives. Harmonic analysis is carried out on the measured line-to-line voltage, stator current, and acoustic noise corresponding to the three methods at different fundamental and carrier frequencies. Based on the magnitude and phase of current harmonics, the frequency and normalized magnitude of dominant magnetic force waves are predicted theoretically. Theoretical predictions and experimental results both show that the magnitudes of dominant acoustic noise components around the carrier frequency are reduced significantly with these BCPWM methods compared with CSVPWM. Furthermore, it is shown that $30^\circ$ BCPWM is better than $60^\circ$ BCPWM in terms of acoustic pleasantness.

Thirteen‐level cascaded H ‐bridge inverter operated by Generic phase shifted pulse‐width modulation

The study proposes a new Generic phase shifted (PS) pulse-width modulation (PWM) approach. Four Generic PS PWM algorithms are proposed. The important advantage of the proposed approach is that it can be easily implemented with multilevel inverters of any topology. The first method produces the 13-level PS PWM signal from six 3-level phase disposition (PD) PWM signals whose carrier signals are PS from each other by the time interval of 1/(6 f carrier ). The second method produces the 13-level PWM signal also from six 3-level PD PWM signals, whereas their modulation and the carrier signals are both PS by the time interval of T modulation /(6 × 5), where T modulation is the modulation cycle time interval. The third method produces the 13-level PWM signal from three 5-level PD PWM signals, whereas their carrier signals are PS from each other by the time interval of 1/(3 f carrier ). The fourth method produces the 13-level PS PWM signal from three 5-level PD PWM signals, whereas their modulation and carrier signals are both PS by the time interval of T modulation /(3 × 5). The proposed methods are analysed and compared one to the other and to the conventional PD PWM method. The analysis is validated by extensive simulation results.

Common-Mode Voltage Reduction Pulsewidth Modulation Techniques for Three-Phase Grid-Connected Converters

This paper experimentally investigates the performance of three-phase voltage source pulsewidth modulation (PWM) converter, with the grid interfaced photovoltaic energy conversion system being the main application. In such applications the ground leakage current [common mode current (CMC)] should be much less than an ampere and this is difficult to obtain in transformerless (direct) connected systems. With the target being the reduction of the common mode voltage (CMV) and CMC, the converter performance is investigated thoroughly. Conventional PWM methods [space vector PWM (SVPWM) and discontinuous PWM (DPWM)] and recently developed reduced common mode voltage PWM (RCMV-PWM) methods [active zero state PWM (AZSPWM) and near state PWM (NSPWM)] are considered. The performance of a 1-kW rated PWM rectifier with additional common-mode capacitor emulating a PV system has been experimentally investigated. It is shown that the CMV and CMC of the tested RCMV-PWM methods is significantly less than conventional methods. In particular, NSPWM yields the best overall performance including low ground leakage current, low inverter output (phase current) and input (dc-link current) ripple, and low switching losses. Accounting for the parasitic capacitance effect, the resonant frequency of the common-mode circuit is identified and it is used in the converter design for the purpose of avoiding resonances involving large CMV-CMC. This paper aims help the design engineer select the appropriate PWM method for grid-connected applications and provides some design rules of thumb.

A Generalized Scalar PWM Approach With Easy Implementation Features for Three-Phase, Three-Wire Voltage-Source Inverters

The generalized scalar pulse width modulation (PWM) approach, which unites the conventional PWM methods and most recently developed reduced common mode voltage PWM methods under one umbrella, is established. Through a detailed example, the procedure to generate the pulse patterns of these PWM methods via the generalized scalar PWM approach is illustrated. With this approach, it becomes an easy task to program the pulse patterns of various high performance PWM methods and benefit from their performance in modern three-phase, three-wire voltage-source inverters for applications such as motor drives, PWM rectifiers, and active filters. The theory is verified by laboratory experiments. Easy and successful implementation of various high-performance PWM methods is illustrated for a motor drive.

Pulsewidth Modulation Method of Matrix Converter for Reducing Output Current Ripple

A matrix converter interfaces with three-phase ac voltage source, which creates three different virtual dc-link voltages. In this paper, a new pulsewidth modulation (PWM) method for the matrix converter is proposed to generally use these three virtual dc-link voltages. By using the two higher line-to-line voltages as the virtual dc-link voltages, the proposed method can create the identical switching sequences to those created by the conventional space vector PWM (SVPWM) method. Moreover, the proposed method is able to select the appropriate virtual dc-link voltage, according to the PWM purpose and/or load condition. In this paper, the virtual dc-link voltages adjacent to the output voltage reference are introduced to reduce output-current switching ripples. The feasibility of the proposed PWM method was verified by a computer simulation and experimental results. The output voltage and current waveforms produced by using the proposed method can be equal or better than those created using the conventional SVPWM method. Moreover, a new switching sequence that reduces output-current switching ripple can be easily adopted within the proposed PWM method. The harmonic characteristics of output current created using the proposed method are markedly improved over those using the conventional PWM method.

A Three-Phase Solar Power Conditioner Using a Single-Phase PWM Control Method

This paper presents the operating performance of a three-phase solar power conditioner using a single-phase pulse-width modulation (PWM) method. The proposed modulation method turns on or off only one of the three phase legs in one PWM-carrier period. The proposed method enables to reduce the average switching frequency by a factor of three, and thus it has a switching power loss four times smaller than a conventional three-phase PWM method does. Experimental results obtained by using a 4-kW, 200-V setup are shown to verify the operating principle and performance. The experimental setup exhibits a high efficiency of 98% and an acceptable total harmonic distortion (THD) as low as 4.1%.

A Near-State PWM Method With Reduced Switching Losses and Reduced Common-Mode Voltage for Three-Phase Voltage Source Inverters

The near-state pulsewidth modulation (NSPWM) method, which reduces the common-mode voltage/current, is proposed for three-phase pulsewidth modulation (PWM) inverter drives. The method is described, its optimal voltage vectors are found, and the sequence that these vectors are applied is determined. Its voltage linearity and DC bus and AC output PWM current ripple characteristics are studied. Its output line-to-line voltage pattern is carefully studied with regard to switching transients that may cause overvoltages at the motor terminals, particularly for long-cable applications. The NSPWM method is thoroughly investigated, and its performance is compared to conventional PWM methods. Theory, simulations, and experiments show that NSPWM exhibits superior common-mode performance and satisfactory input/output PWM ripple performance characteristics. It is also illustrated that even though the method has bipolar line-to-line output voltage pulses, due to the sufficient zero-voltage time intervals for the switching transients to settle, these pulses do not cause additional overvoltages at the motor terminals compared to the conventional methods. The method is feasible for motor drives, particularly for operation in the high modulation index range, where its overall performance exceeds the performances of the state-of-the-art PWM methods.