Conventional Pulse Frequency Modulation Research Articles

Hybrid Control for Three-Level LLC Resonant Converter of Dual-Bridge for Wide Output Range

A three-level (TL) LLC resonant converter of dual-bridge (DB) with hybrid control modulation strategy is proposed for the wide output-voltage range and high input-voltage applications. The topology integrates two neutral-point-clamped arms (NPCs) through an auxiliary transformer, which forms a new controllable double-voltage structure and makes all MOSFETs hold half of the input voltage. Based on the characteristics of the new topology, a hybrid modulation strategy is proposed corresponding to three gain modes, which include conventional pulse frequency modulation (PFM) and fixed frequency phase shift modulation (FF-PSM). Compared to conventional modulation strategies, the proposed hybrid modulation strategy, which improves the output voltage gain range, achieves zero-voltage switching (ZVS) of all the MOSFETs and zero-current switching (ZCS) of rectifier diodes under wider operating voltage and full load range. To minimize the frequency window and improve the efficiency of the converter, the parameter optimization method is designed, which based on the characteristics of the modulation strategy and the relationship among the maximum output voltage gain, resonant current and turned-off current. At last, the experimental results of the 600W prototype are presented to confirm the theoretical and characterization analysis.

高周波IH応用単相ダイレクトAC-ACコンバータの固定周波数電力制御手法

The direct ac-ac converter is an effective circuit topology for high-efficient power conversion in induction heating (IH) applications. The conventional pulse frequency modulation (PFM)-based power control scheme causes audible noises between the adjacent IH loads which operate at different switching frequencies. As a solution for the technical issue, a new fixed-frequency power control methodology for a single-phase direct ac-ac converter is proposed in this paper, featuring a wide range of soft switching operation and robustness for abnormal load conditions. The principle of the proposed pulse modulation is explained in detail with the logic circuit diagram of controller. The performances of the ac-ac converter and power controller are demonstrated by simulation, after which the effectiveness is revealed in terms of the power control range and soft switching operation.

A Bidirectional Synchronous/Asynchronous Rectifier Control for Wide Battery Voltage Range in SiC Bidirectional LLC Chargers

Conventional pulse frequency modulation is typically adopted in the reverse <i>LLC</i> converter resulting in a low voltage gain. The output bus voltage may be lower than peak grid voltage, so that the buck-type inverter cannot output 220 Vac and poses series challenge to achieve bidirectional charger operation. A bidirectional synchronous&#x002F;asynchronous rectifier control is proposed for wide battery voltage applications in the <i>LLC</i> converter. In the forward mode, a simplified model is built to calculate the synchronous rectifier (SR) on-time and achieve high efficiency by using a two-order function. In the reverse mode, the turn-<small>on</small> instants of primary side and secondary side power devices are controlled with a delay angle to obtain high voltage gain and high efficiency. A 6.6-kW silicon carbide bidirectional <i>LLC</i> charger was built. With the proposed SR control, the forward <i>LLC</i> efficiency improves 0.2&#x0025; compared with the conventional SR method. The reverse <i>LLC</i> voltage gain is up to 1.33 so that the charger can output 220 Vac in the full battery voltage range of 200&#x2013;500 V.

A Fully Integrated 10-V Pulse Driver Using Multiband Pulse-Frequency Modulation in 65-nm CMOS

This brief describes a fully integrated 10-V pulse driver. It comprises a four-stage switched-capacitor voltage multiplier (SCVM) and a dedicated high-voltage output driver (HVOD) with multiband pulse-frequency modulation (MPFM) to generate efficiently 10 V regulated output pulses. Specifically, an analog/digital hybrid-controlled current-starved ring oscillator (HCRO) modulates the switching frequencies at distinct bands to regulate the high-voltage (HV) supply for the HVOD, while enabling fast output transitions with an improved driving efficiency. Prototyped in 65-nm bulk CMOS, the driver demonstrates 10-V pulse generations over a 0.1-to-1-MHz range for a 15 pF//50 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{k}\Omega $ </tex-math></inline-formula> load. With the proposed MPFM, this work measures an overall driving efficiency of up to 19.9%, corresponding to a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 1.6\times $ </tex-math></inline-formula> improvement over prior arts. The measured output rise time of 119 ns is also ~25% faster when compared with using the conventional pulse-frequency modulation (PFM) scheme.

Hybrid Control Strategy for LLC Converter With Reduced Switching Frequency Range and Circulating Current for Hold-Up Time Operation

Hold-up time operation is a crucial requirement for distributed power systems and server power supplies. LLC resonant converter is widely used in these applications due to its high efficiency and power density characteristics. Conventional pulse frequency modulation (PFM)-controlled inductor-inductor-capacitor (LLC) resonant converter requires a wide switching frequency operation range to satisfy the hold-up requirement. In this article, a novel control scheme is proposed for stacked structure LLC resonant converter. During the normal operation, the frequency doubler modulation strategy is adopted to reduce the switching loss and driving loss, and the output is regulated by PFM. During the hold-up time operation, the pulsewidth modulation is adopted to increase the system voltage gain, where the switching frequency is fixed during this operation stage. For the proposed converter, the resonant tank parameters are designed at the nominal operation point, and the only design consideration for the magnetizing inductor is the zero-voltage switching for primary switches. Therefore, compared with PFM-LLC, both the switching frequency operating range and the circulating current are reduced, and high efficiency feature is obtained. Finally, a 100-W experimental prototype with input voltage range of 160-340 V was built to validate the advantages of the proposed converter.

Optimization of LLC Resonant Converter With Two Degrees of Freedom Based on Operation Stage Trajectory Analysis

LLC resonant DC-DC converter has been widely used in high power density and high efficiency applications. Pulse frequency modulation (PFM) is commonly applied due to its wide soft-switching range. In some special cases, phase shift modulation (PSM) is applied to widen voltage regulation range, improve light-load efficiency, or implement a soft start-up process. Because LLC is with 2 control degrees of freedom (2DOFs), switching frequency and duty ratio, a unified analysis and optimization for LLC with 2DOFs is desired. This paper makes an effort to present a unified time domain operation stage trajectories (OSTs) analysis of LLC. On this basis, a unified numerical optimization method is proposed with arbitrarily designed optimization objectives. With the proposed optimization method, the optimized LLC with 2DOFs is with better performance compared to conventional PFM and PSM, which is verified by the experimental results.

Analysis and design of LLC resonant converter with variable magnetising inductance control

A conventional pulse frequency modulation (PFM) controlled LLC resonant converter requires a wide switching frequency operating range to regulate the output voltage. There are some disadvantages of PFM LLC resonant converters: (i) the design and optimisation of magnetic components and gate driver circuitry are challenging; (ii) due to the variable switching frequency operating range, electro-magnetic interference performance of the converter is degraded; (iii) efficiency degradation; (iv) inability to achieve independent control in multiple-output applications. To address the above-mentioned problems and achieve fixed switching frequency operation, a variable magnetising inductance control (VMIC) strategy is proposed. In the proposed VMIC control strategy, the operating switching frequency of the primary switch is fixed and the duty cycle remains constant at 0.5. At the resonant frequency operating point, the output voltage is independent of both the magnetising inductance and load. In addition, the zero current turn-off operation of the secondary rectifier requires that the switching frequency be designed below the resonant frequency. The operational principles and design considerations of the LLC resonant converter with VMIC are presented. Experimental results from a 200 W prototype are presented to validate the theoretical analysis and the effectiveness of the proposed VMIC control strategy.

A Novel Hybrid PFM/IAPWM Control Strategy and Optimal Design for Single-Stage Interleaved Boost-LLC AC–DC Converter With Quasi-Constant Bus Voltage

Single-stage boost-LLC ac-dc converters have been a popular soft-switched topology because of the high-efficiency and being cost-effective. However, low power capacity is its main disadvantage. In this article, a novel single-stage interleaved boost-LLC ac-dc converter with higher power capacity is presented while achieving the low input current ripple. However, it still suffers from the wide and high bus voltage for universal operation, as a result of the conventional pulse frequency modulation (PFM) with the duty cycle of 0.5. Furthermore, this wide bus voltage will bring the difficulties in designing the LLC resonant cell. To solve these issues, a dual-loop feedback control strategy based on PFM/interleaved asymmetric pulsewidth modulation hybrid modulation and power balance based optimal design are proposed. With the proposed control strategy and optimal design, the bus voltage of the studied converter is not only significantly reduced, but also zero voltage switching for the primary switches and zero current switching for the secondary diodes are still maintained. Thus, the higher efficiency can be achieved. Operation principles and control scheme for the studied converter are fully addressed. The optimal design based on power balance principle is also discussed in this article. A 300 W prototype is fabricated to validate the theoretical analysis and optimal design. The experimental results demonstrate the prototype can simultaneously obtain the universal operation with high power factor above 0.98 and the quasi-constant bus voltage below 500 V. The measured peak efficiency is 92.7% under 115 Vac input voltage at full load.

Burst-Mode and Phase-Shift Hybrid Control Method of LLC Converters for Wide Output Range Applications

For an LLC converter, it is difficult to realize the wide output range with conventional pulse frequency modulation control because of the limited operating frequency. This paper proposes a new hybrid control method. The proposed strategy combines the burst-mode control and phase-shift control methods for the LLC converter. The burst-mode control can regulate the output voltage from zero to its maximum value, and the phase-shift control can reduce the increased resonant current during burst-on time. By using this method, the wide output voltage range is realized with the low resonant current during burst-on time and zero-voltage switch (ZVS) for all switches. The reliability and efficiency of the converter can be improved accordingly. The burst duty ratio is regulated by the reference output voltage, and the phase-shift angle is derived when realizing ZVS for lagging-leg switches. Moreover, the resonant parameters and the maximum phase-shift angle are optimized under the constraints of current stress and ZVS condition. This method is easy to be implemented in a low-cost microcontroller because high-frequency real-time calculations are not necessary. A 1.5-kW prototype is built to verify the feasibility and validity of the proposed control method.

A CMOS PFM buck converter employing a digitally programmable voltage level-shifting technique

This paper describes a CMOS pulse frequency modulation (PFM) buck converter employing a digitally programmable voltage level-shifting technique capable of adjusting peak inductor current and output ripple voltage for different load currents. The conventional PFM buck converters employ either an adaptive delay time control circuit or a fixed delay time control circuit to control output ripple voltage and power efficiency with the switching frequency. However, they suffer from a large peak inductor current, resulting in reduced power efficiency. The digitally programmable voltage level-shifting circuit, based on a common source amplifier, is capable of sensing inductor current through the voltage drop caused by on-resistance of the power switch, and can control peak inductor current. The precision needed to control the magnitude of the peak inductor current can be obtained with the number of bits in the digitally programmable voltage level-shifting circuit that are dependent on the input common mode range of the comparator. Employment of one comparator with pre-control logic and post-control logic circuits allows the proposed circuit to improve power efficiency by removing additional circuits, compared with the conventional PFM buck converters. The proposed converter was implemented with a 180 nm CMOS process. The effective chip size of the core block occupies 900μm × 590μm. The proposed PFM mode buck converter with a precision of four bits to control peak inductor current is capable of accommodating an input voltage range of 2.7–3.3 V, and can produce output voltage of 1.2 V. The operational switching frequency measured is on the order of several to several hundred kHz, the load current range is under 150 mA, and the measured output ripple voltage varied, depending on the digital programming status. The measured power efficiency ranged between 70 and 84%.

A Single-Stage PFM-APWM Hybrid Modulated Soft-Switched Converter With Low Bus Voltage for High-Power LED Lighting Applications

In order to design a high-efficiency cost-effective high-power LED driver, a single-stage integrated boost- LLC -type soft-switched ac–dc converter is usually employed. The minimized number of semiconductors and the reduced power loss are its main advantages. However, the high bus voltage is its well-known disadvantage, which is caused by the employment of a conventional pulse frequency modulation (PFM) control strategy with the duty cycle of 0.5. The range of the input ac voltage is severely limited. In order to overcome this problem, a hybrid PFM-asymmetric pulse width modulation strategy is proposed in this paper. The proposed strategy can significantly reduce the bus voltage while maintaining the soft-switching operation for both primary MOSFETs and secondary diodes. Furthermore, the electrolytic capacitors are removed by increasing the bus voltage ripple. Hence, high efficiency, long lifetime, low cost, and universal operation are achieved on the proposed LED driver, which is well matched to the virtues of LED lighting source. The detailed operation principles and design consideration for the proposed modulation approach are analyzed and discussed. The feature of the proposed solution was demonstrated using a universal-input 100-W hardware prototype. The experimental results verified the full-range zero-voltage-switching (ZVS) operation for primary switches and the efficiency achieved 91.6% under the 130-V input voltage.

PWM and PFM Hybrid Control Method for LLC Resonant Converters in High Switching Frequency Operation

High switching frequency is an effective method to improve power density for LLC resonant converters. However, conventional digital controllers, such as general-purpose digital signal processors and microprocessors, have limited frequency resolution, which induces high primary- and secondary-side current variation and leads to poor output voltage regulation. In this paper, a hybrid control method combining pulse frequency modulation (PFM) and pulse width modulation is proposed to overcome the limited frequency resolution issue. The proposed hybrid control method focuses on steady-state operation, and its operating principles are introduced and analyzed. In addition, the proper magnetizing inductance and dead time duration are derived to ensure that the power mosfet s achieve zero voltage switching with the proposed control method. The improved voltage regulation performance is compared with the conventional PFM control and verified through simulation and experimental results using a 240 W prototype converter operating at a switching frequency of 1 MHz.

Digital readout integrated circuit (DROIC) implementing time delay and integration (TDI) for scanning type infrared focal plane arrays (IRFPAs)

This paper presents a digital readout integrated circuit (DROIC) implementing time delay and integration (TDI) for scanning type infrared focal plane arrays (IRFPAs) with a charge handling capacity of 44.8Me− while achieving quantization noise of 198e− and power consumption of 14.35mW. Conventional pulse frequency modulation (PFM) method is supported by a single slope ramp ADC technique to have a very low quantization noise together with a low power consumption. The proposed digital TDI ROIC converts the photocurrent into digital domain in two phases; in the first phase, most significant bits (MSBs) are generated by the conventional PFM technique in the charge domain, while in the second phase least significant bits (LSBs) are generated by a single slope ramp ADC in the time domain. A 90×8 prototype has been fabricated and verified, showing a significantly improved signal-to-noise ratio (SNR) of 51dB for low illumination levels (280,000 collected electrons), which is attributed to the TDI implementation method and very low quantization noise due to the single slope ADC implemented for LSBs. Proposed digital TDI ROIC proves the benefit of digital readouts for scanning arrays enabling smaller pixel pitches, better SNR for the low illumination levels and lower power consumption compared to analog TDI readouts for scanning arrays.