Conventional Low-density Parity-check Research Articles

Energy-Efficient Partial LDPC Decoding for NAND Flash-Based Storage Systems

A new decoding method for low-density parity-check (LDPC) codes is presented to lower the energy consumption of LDPC decoders for NAND flash-based storage systems. Since the channel condition of NAND flash memory is reliable for most of its lifetime, it is inefficient to apply the maximum-effort decoding with the full parity-check matrix (H-matrix) from the beginning of the lifespan. As the energy consumption and the decoding latency are proportional to the size of the H-matrix used in decoding, the proposed algorithm starts the decoding with a partial H-matrix selected by considering the channel condition. In addition, the proposed partial decoding provides various error-correcting capabilities by adjusting the partial H-matrix. Based on the proposed partial decoding algorithm, a prototype decoder is implemented in a 65 nm CMOS process to decode a 4 KB LDPC code. The proposed decoder reduces energy consumption by 93% compared to the conventional LDPC decoding architecture at maximum.

Novel intelligent blind information reconciliation for LDPC codes in quantum key distribution systems

Information reconciliation is an important step in quantum key distribution (QKD). As a good channel coding technology, LDPC (low-density parity-check) code perform well in information reconciliation. In this paper, we investigate a new approach, namely blind information reconciliation. In our approach, after the state distribution is carried out by Alice and the measurements are taken by Bob, Alice can select an appropriate LDPC encoder (parity-check matrix) from the predefined candidate pool according to the estimated QBER (quantum bit-error-rate). Bob can use the expectation–maximization (EM) estimator and the maximum average log-likelihood ratio (LLR) detector to blindly identify parity-check matrices associated with not only different code-rates but also different codeword-lengths Alice employed. Moreover, puncturing and shortening can also be invoked to adjust the code-rate slightly to improve the error-correction performance. Monte Carlo simulations have demonstrated that our proposed new blind information-reconciliation scheme can successfully identify the parity-check matrix even under high QBER conditions, reduce the interactive communication-rounds, and improve the reconciliation efficiency in comparison with the conventional rate-adaptive LDPC coding scheme without QBER estimation.

Short-Block-Length Low-Density Parity-Check Codes-Based Underwater Acoustic Spread-Spectrum Communication System

Low-density parity-check (LDPC) codes are commonly used in communication systems to improve the system performance, but LDPC codes takes too long for decoding, making communication inefficient and unsuitable for short-frame data transmission methods. In underwater acoustic channels, spread-spectrum communication becomes an effective way to realize long-distance communication. This paper combines short-block LDPC codes with a direct sequence spread spectrum and soft spread spectrum in underwater acoustic communication, addressing the problem of the inapplicability of conventional LDPC codes. The applicability of the proposed method in this paper is verified through simulation tests and pool experiments. The results indicate that the proposed communication system achieves lower bit error rates compared to the classical coding methods used in underwater acoustic spread-spectrum communication systems under the same channel conditions.

Monitor Units Assisted LDPC Decoding Algorithm based on Page BER Variation of 3D NAND Flash Memory

With the increase of retention time and program/erase (P/E) cycles, the reliability of 3D NAND Flash memory with large storage capacity degrades. Because of its excellent error correction capability, the low density parity check (LDPC) code has become the mainstream method for solving reliability problems in modern NAND Flash memory. However, the log-likelihood ratio (LLR) obtained by the conventional scheme is not accurate enough to guarantee decoding performance. Moreover, page bit error rate (BER) variation exacerbates LLR inaccuracy. To solve these problems, we propose a Monitor-Units BER Calibrated LDPC (MBCL) algorithm, which adds additional data as monitor units (MUs) to monitor the change of BER in pages and get more accurate LLR values. On this basis, we propose an All State BER Estimation LDPC (ABEL) algorithm to utilize the BER obtained by MUs to estimate the BER of all other voltage states. It reduces the storage overhead of the MBCL algorithm. Compared with the conventional LDPC scheme, the proposed algorithms extend the lifetime by up to 5.83 times and reduce the decoding iterations by up to 78.63%.

Fast phase error correction with reference beam-assisted LDPC coding for collinear holographic data storage.

Low-density parity-check (LDPC) coding is a significant technique for ensuring data reliability in phase-modulated holographic data storage. To accelerate LDPC decoding, we design reference beam-assisted LDPC coding for 4-level phase-modulated holography. The reliability of a reference bit is higher than that of an information bit during decoding because reference data are known during recording and reading processes. By considering the reference data as prior information, the weight of the initial decoding information (i.e., log-likelihood ratio (LLR) information) of the reference bit is increased during LDPC decoding. The performance of the proposed method is evaluated through simulations and experiments. In the simulation, compared with the conventional LDPC code with a phase error rate (PER) of 0.019, the proposed method can reduce bit error rate (BER) by 38.8%, uncorrectable bit error rate (UBER) by 24.9%, decoding iteration time by 29.9%, the number of decoding iterations by 14.8%, and improve decoding success probability by 38.4% approximately. Experimental results demonstrate the superiority of the proposed reference beam-assisted LDPC coding. The developed method can significantly decrease the PER, BER, the number of decoding iterations, and decoding time by using the real captured images.

Free-Ride Feedback and Superposition Retransmission Over LDPC Coded Links

In this paper, we propose a new transmission scheme for the scenario where two nodes attempt to exchange messages and the conventional low-density parity-check (LDPC) codes are implemented for error correction. In the proposed scheme, the ACK/NACK feedback information is transmitted along with the payload data by free-ride codes, while the re-transmitted codewords are superimposed (XORed) on the current codewords, both of which cost neither extra bandwidth nor transmission power. Firstly, we present a syndrome channel model and derive its capacity (referred to as accessible capacity) with a lower bound, implying that the reliable transmission of extra bits (feedback information) is possible. Then, the performance of the extra bits is analyzed by the dependency testing (DT) bound for the syndrome channels. Moreover, motivated by the DT bound, we present a low-complexity DT-like decoder for the free-ride codes. For the superposition retransmission, we present a practical implementation, where those unsuccessfully decoded codewords are sparsely interleaved and superimposed onto the current codewords. In addition, the presented transmission scheme is combined with the conventional hybrid automatic repeat request (HARQ) protocol, resulting in a throughput-enhanced conjunction HARQ scheme. Numerical results show that the word error rate (WER) of the LDPC codes can be significantly reduced by using the presented transmission scheme, but without any extra bandwidth or transmission power. They also show that the presented conjunction HARQ schemes can achieve a throughput improvement up to 80% over fading channels in comparison with the original 5G HARQ scheme.

Beyond 100 Gbit/s Pipeline Decoders for Spatially Coupled LDPC Codes

Low-density parity-check (LDPC) codes are a well-established class of forward error correction codes that provide excellent error correction performance for large code block sizes. However, for throughputs toward 1 Tbit/s, as expected for B5G systems, state-of-the-art LDPC soft decoders are restricted to short code block sizes of several hundred to thousands of bits due to routing congestion challenges, limiting the overall communications performance of the transmission system. Spatially coupled LDPC (SC-LDPC) codes and respective sliding window decoding methods show the potential to overcome these block size restrictions. However, in contrast to conventional LDPC codes little literature exists on the efficient hardware implementation of respective high-throughput decoders. In this work, we present the first in-depth investigation on the implementation of SC-LDPC decoders for throughputs beyond 100 Gbit/s. For an N=51328, R=0.8 terminated SC-LDPC code with sub-block size c=640 and coupling width m_s=1, we explore various design trade-offs, including row- and column-wise decoding, non-overlapping and overlapping window scheduling, and processor pipelining. To the best of our knowledge, this is the first description of a column-wise SC-LDPC decoding architecture in the literature. We complement the algorithmic investigation with the virtual silicon implementation of all presented decoders in a 22nm FD-SOI technology.

Design of Protograph-Based LDPC Codes for Two-User Gaussian Multiple Access Channel

In this letter, we study the performance of protograph-based low-density parity-check (LDPC) codes for two-user Gaussian multiple access channel (GMAC). Considering the characteristic of a joint protograph of two users, we first derive a joint protograph-based extrinsic information transfer (JP-EXIT) chart to analyze the iterative user decoding behavior of two-user GMAC. Guided by the JP-EXIT, we further propose a new design scheme and construct protograph base matrices of different code rates for two users, respectively. Both theoretical analyses and simulation results show that the proposed protograph-based LDPC codes of low decoding threshold outperform the conventional irregular LDPC codes for both equal-power and unequal-power GMAC with different code rates.

Network coding schemes with efficient LDPC coded MIMO–NOMA in two‐way relay networks

The combination of non-orthogonal multiple access (NOMA) and multi-input multi-output (MIMO) approaches has been considered as assuring multiple access for the fifth generation technology. In this study, the performance of a 2 × 2 MIMO–NOMA system with low-density parity check (LDPC) codes is investigated. Redundancy with randomly interleaved differential encoding (R-RIDE) is proposed and applied to LDPC encoded messages by two users. LDPC decoding is done using the sum-product algorithm (SPA), which has two types of decoding methods, hard-decision and soft-decision. For hard-decision, bit-flipping decoder is used and for soft-decision, probability domain, log-domain, and simplified log-domain decoders are used. Bit error rate (BER) versus signal-to-noise ratio (SNR) in (dB) and average mutual information (AMI) in (bps/Hz) versus SNR (dB) are evaluated to compare the performance of the proposed and conventional LDPC schemes in NOMA and MIMO–NOMA systems. Simulation results show that both AMI and BER of the proposed LDPC–R-RIDE in MIMO–NOMA system greatly outperforms conventional LDPC coded schemes in NOMA and MIMO–NOMA systems. Moreover, the proposed R-RIDE-LDPC in MIMO-NOMA system outperforms the proposed scheme in the NOMA system. From the simulation results, LDPC–R-RIDE with simplified log-domain decoder has the best AMI result and BER performance compared with other decoding methods.

Pair-Bit Errors Aware LDPC Decoding in MLC NAND Flash Memory

By storing multibit per cell, multilevel cell (MLC) NAND flash memory achieves high storage capacity, but sacrificing data reliability. Error correction codes, such as Bose–Chaudhuri–Hocquenghem (BCH) codes, are widely used to ensure data reliability. However, high raw bit error rates induced by interference noises make BCH codes become insufficient to guarantee data reliability. Low-density parity-check (LDPC) codes are considered as the replacement due to the stronger error correction capability. Nevertheless, directly exploiting LDPC codes introduces a concern about decoding latency because of their iterative decoding in the soft decision process. To develop effective LDPC decoding algorithms, it is necessary to have a more profound understanding on flash failure patterns. This paper first observes the pair-bit errors (PBEs) characteristic of MLC NAND flash memory on a real field-programmable gate array testing platform, then proposes a PBE-aware LDPC (PAL) decoding scheme-based upon this observation, in which PBE provides the promotion information for LDPC decoding to reduce decoding latency. Simulation results show that the decoding latency can be reduced by up to 54%, compared with the conventional LDPC codes.

Packing additional bits into LDPC coded data

In this Letter, the authors proposed a novel scheme, with neither extra transmission energy nor extra bandwidth, to transmit additional bits along with low-density parity-check (LDPC) coded payload data. At the transmitter, additional bits are first transformed into a random-like sequence, which is then superimposed onto the LDPC coded data, resulting in the transmitted sequence. At the receiver, a statistical learning-based algorithm is employed to detect the additional bits. Then the interference of the additional bits is removed and the payload data is recovered by the conventional LDPC decoder. Simulation results show that, for a (3,6)-regular LDPC code of length 8064, ten additional bits can be transmitted reliably with negligible effect on the reliability of the payload data.

Quasi-Cyclic Spatially Coupled LDPC Code for Broadcasting

Flexible and robust transmission schemes are required to support different coded modulation modes, receiver types and channel conditions in future broadcasting systems. However, conventional low-density parity-check (LDPC) coded schemes are usually optimized towards particular scenario, and may face the problem of performance degradation in other different scenarios. In this paper, a type of quasi-cyclic spatially coupled LDPC (QC-SC-LDPC) codes, which have been recently proven to be able to universally achieve capacity over different channels under conventional belief propagation decoding, are proposed as the forward error correcting codes for broadcasting applications. Then a QC-SC-LDPC coded transmission scheme is proposed, which is capable of showing good performance in various scenarios under practical constraints of finite coupling length, smoothing parameter, uncoupled code length and number of decoding iterations. To maintain the universal property under the above constraints, a typical construction method is developed, based on which a QC-SC-LDPC code is constructed as an example. Finally, the performance and robustness of the proposed QC-SC-LDPC coded transmission scheme are demonstrated via simulations under different yet typical coded modulation modes and channel conditions.

LDPC Coded Massive MIMO Systems.

We design a coded massive multiple-input multiple-output (MIMO) system using low-density parity-check (LDPC) codes and iterative joint detection and decoding (JDD) algorithm employing a low complexity detection. We introduce the factor graph representation of the LDPC coded massive MIMO system, based on which the message updating rule in the JDD is defined. We devise a tool for analyzing extrinsic information transfer (EXIT) characteristics of messages flowing in the JDD and the three-dimensional (3-D) EXIT chart provides a visualization of the JDD behavior. Based on the proposed 3-D EXIT analysis, we design jointly the degree distribution of irregular LDPC codes and the JDD strategy for the coded massive MIMO system. The JDD strategy was determined to achieve a higher error correction capability with a given amount of computational complexity. It was observed that the coded massive MIMO system equipped with the proposed LDPC codes and the proposed JDD strategy has lower bit error rate than conventional LDPC coded massive MIMO systems.

LDPC coding scheme for improving the reliability of multi-level-cell NAND flash memory in radiation environments

Utilizing commercial off-the-shelf (COTS) components in satellites has received much attention due to the low cost. However, commercial memories suffer severe reliability problems in radiation environments. This paper studies the low-density parity-check (LDPC) coding scheme for improving the reliability of multi-level-cell (MLC) NAND Flash memory in radiation environments. Firstly, based on existing physical experiment works, we introduce a new error model for heavy-ion irradiations; secondly, we explore the optimization of writing voltage allocation to maximize the capacity of the storage channel; thirdly, we design the degree distribution of LDPC codes that is specially suitable for the proposed model; finally, we propose a joint detection-decoding scheme based on LDPC codes, which estimates the storage channel state and executes an adaptive log-likelihood ratio (LLR) calculation to achieve better performance. Simulation results show that, compared with the conventional LDPC coding scheme, the proposed scheme may almost double the lifetime of the MLC NAND Flash memory in radiation environments.

Optimization of LDPC Codes for PIN-Based OOK FSO Communication Systems

For middle/short-range terrestrial high-speed free-space optical (FSO) communication systems employing ON–OFF keying (OOK) and PIN photodiode receivers, the noise distribution is symbol-dependent, and the symmetry of the underlying communication channel cannot be assumed. Therefore, this letter employs the asymmetric density evolution technique and an optimization scheme combining four different search algorithms to optimize low-density parity-check (LDPC) codes for these FSO systems. Compared with the conventional LDPC codes that are designed assuming symbols-independent symmetric channels the optimized codes are much closer to the Shannon limit for OOK modulated binary non-symmetric channels.

Received response based heuristic LDPC code for short-range non-line-of-sight ultraviolet communication.

Through slight modification on typical photon multiplier tube (PMT) receiver output statistics, a generalized received response model considering both scattered propagation and random detection is presented to investigate the impact of inter-symbol interference (ISI) on link data rate of short-range non-line-of-sight (NLOS) ultraviolet communication. Good agreement with the experimental results by numerical simulation is shown. Based on the received response characteristics, a heuristic check matrix construction algorithm of low-density-parity-check (LDPC) code is further proposed to approach the data rate bound derived in a delayed sampling (DS) binary pulse position modulation (PPM) system. Compared to conventional LDPC coding methods, better bit error ratio (BER) below 1E-05 is achieved for short-range NLOS UVC systems operating at data rate of 2Mbps.

Capacity-Approaching TQC-LDPC Convolutional Codes Enabling Power-Efficient Decoders

In this paper, we develop a new capacity-approaching code, namely, parallel-concatenated (PC)-Low Density Parity Check (LDPC) convolutional code that is based on the parallel concatenation of trellis-based quasi-cyclic LDPC (TQC-LDPC) convolutional codes. The proposed PC-LDPC convolutional code can be derived from any QC-LDPC block code by introducing the trellis-based convolutional dependency to the code. The capacity-approaching PC-LDPC convolutional codes are encoded through parallel concatenated trellis-based QC recursive systematic convolutional (RSC) encoder (namely, QC-RSC encoder) that is also proposed in this paper. The proposed PC-LDPC convolutional code and the associated encoder retain a fine input granularity on the order of the lifting factor of the underlying block code. We also describe the corresponding trellis-based QC maximum a posteriori probability (namely, QC-MAP) decoder that efficiently decodes the PC-LDPC convolutional code. Performance and hardware implementation results show that the PC-LDPC convolutional codes with the QC-MAP decoder have two times lower complexity for a given bit-error-rate (BER), signal-to-noise ratio, and data rate, than conventional QC-LDPC block codes and LDPC convolutional codes. Moreover, the PC-LDPC convolutional code with the QC-MAP decoder outperforms the conventional QC-LDPC block codes by more than 0.5 dB for a given BER, complexity, and data rate and approaches Shannon capacity limit with a gap smaller than 1.25 dB. This low decoding complexity and the fine granularity make it feasible to efficiently implement the proposed capacity-approaching PC-LDPC convolutional code and the associated trellis-based QC-MAP decoder in next generation ultra-high data rate mobile systems.

Spinstand demonstration of areal density enhancement using two-dimensional magnetic recording (invited)

Exponential growth of the areal density has driven the magnetic recording industry for almost sixty years. But now areal density growth is slowing down, suggesting that current technologies are reaching their fundamental limit. The next generation of recording technologies, namely, energy-assisted writing and bit-patterned media, remains just over the horizon. Two-Dimensional Magnetic Recording (TDMR) is a promising new approach, enabling continued areal density growth with only modest changes to the heads and recording electronics. We demonstrate a first generation implementation of TDMR by using a dual-element read sensor to improve the recovery of data encoded by a conventional low-density parity-check (LDPC) channel. The signals are combined with a 2D equalizer into a single modified waveform that is decoded by a standard LDPC channel. Our detection hardware can perform simultaneous measurement of the pre- and post-combined error rate information, allowing one set of measurements to assess the absolute areal density capability of the TDMR system as well as the gain over a conventional shingled magnetic recording system with identical components. We discuss areal density measurements using this hardware and demonstrate gains exceeding five percent based on experimental dual reader components.

A Survey on Protograph LDPC Codes and Their Applications

Low-density parity-check (LDPC) codes have attracted much attention over the past two decades since they can asymptotically approach the Shannon capacity in a variety of data transmission and storage scenarios. As a type of promising structured LDPC codes, the protograph LDPC codes not only inherit the advantage of conventional LDPC codes, i.e., excellent error performance, but also possess simple representations to realize fast encoding and efficient decoding. This paper provides a comprehensive survey on the state-of-the-art in protograph LDPC code design and analysis for different channel conditions, including the additive white Gaussian noise (AWGN) channels, fading channels, partial response (PR) channels, and Poisson pulse-position modulation (PPM) channels. Moreover, the applications of protograph LDPC codes to joint source-and-channel coding (JSCC) and joint channel-and-physical-layer-network coding (JCPNC) are reviewed and studied. In particular, we focus our attention on the encoding design and assume the decoder is implemented by the belief propagation (BP) algorithm. Hopefully, this survey may facilitate research in this area.

Conditional termination check min-sum algorithm for efficient LDPC decoders

Conditional termination check min-sum algorithm (MSA) using the difference of the first two minima is proposed for faster decoding speed and lower power consumption of low-density parity-check (LDPC) code decoders. Judging from the size of the difference in LDPC decoding scheduling, the proposed method dynamically decides whether the termination checking steps will be skipped or not. The simulation results show that the decoding speed is improved up to 7%, and the power consumption is reduced by up to 16.43% without any loss of error correcting performance. Also, the additional hardware cost of the proposed method is negligible compared to conventional LDPC decoders.