Conventional DTL Research Articles

Convergence behavior of the first-order time-delay digital tanlock loop

Convergence behavior of the previously proposed time-delay digital tanlock loop (TDTL) is analyzed. The approach is built on the actual number of steps required for the convergence of the phase error to its steady-state value. Unlike the first-order conventional digital tanlock loop (CDTL), the Lipschitz bound of TDTL is not a tight limit for the actual convergence time, especially for higher values of the absolute difference between the initial and the steady-state phase errors. For a frequency step input, the first-order TDTL locks faster than CDTL under suitable arrangement of the loop parameters.

A time-delay digital tanlock loop

We propose a nonuniform sampling digital tanlock loop (DTL) that utilizes a constant time-delay unit instead of the constant 90/spl deg/ phase shifter The new structure reduces the complexity of implementation and avoids many of the practical problems associated with the digital Hilbert transformer like the approximations and frequency limitations. The time-delay digital tanlock loop (TDTL) preserves the most important features of the conventional DTL (CDTL), such as reduced sensitivity to the variation of the signal power. It also introduces improvement over the first-order CDTL under suitable choice of the circuit parameters. The first- and second-order loops are analyzed for locking conditions and steady-state phase error.

On improving the performance of a digital tanlock loop

This letter presents an improved digital tanlock loop (DTL) based on a multi-sampling scheme. It yields extended locking range, and reduced steady-state mean and variance of phase error as compared to the conventional DTL. The performance of the first-order DTL is analyzed in the presence of white Gaussian noise, and compared to the conventional DTL.