Conventional Digital Phase-locked Loop Research Articles

Table-Based Adaptive Digital Phase-Locked Loop for GNSS Receivers Operating in Moon Exploration Missions.

An adaptive digital phase-locked loop (DPLL) continually adjusts the noise bandwidth of the loop filter in global navigation satellite system (GNSS) receivers to track signals by measuring the signal-to-noise ratio and/or dynamic stress. Such DPLLs have a relatively large amount of computational complexity compared with the conventional DPLL. A table-based adaptive DPLL is proposed that adjusts the noise bandwidth value by extracting it from the pre-generated table without additional calculations. The values of the noise bandwidth table are computed in an optimal manner in consideration of the thermal noise, oscillator phase noise, and dynamic stress error. The calculation method of the proper integration time to maintain the stability of the loop filter is presented. Additionally, the simulation is configured using the trajectory analysis results from the Moon exploration mission and shows that the proposed algorithm operates stably in harsh environments, while a conventional fixed bandwidth loop cannot. The proposed algorithm has a similar phase jitter performance to the existing adaptive DPLL algorithms and has an execution time that is approximately 2.4-5.4 times faster. It is verified that the proposed algorithm is computationally efficient while maintaining jitter performance.

A 5 GHz Fractional-<inline-formula> <tex-math notation="LaTeX">$N$</tex-math> </inline-formula> ADC-Based Digital Phase-Locked Loops With −243.8 dB FOM

An ADC-based digital phase-locked loop (DPLL) assisted by a digital-to-time converter (DTC) is proposed for fractional- $N$ frequency synthesis. A successive approximation register (SAR) ADC is adopted to mimic the operation of the time-to-digital converter (TDC) in the conventional DPLL to achieve an equivalent 1-ps time-domain resolution. The superiority of ADC-based TDC is revealed and compared to delay-based TDC. The nonlinearity error induced by both TDC and DTC is also analyzed and discussed. Fabricated in a 40 nm CMOS technology, the proposed DPLL achieves an in-band phase noise $-$ 104 dBc/Hz and an integrated phase noise 379 $\text{fs}_{\mathrm{rms}}$ in the fractional- $N$ mode. The DPLL operates at 5 GHz with 2.92-mW power dissipation from a 0.9-V power supply. The core parts only occupy 0.09-mm2 active area. The FoM of the DPLL can be as good as $-$ 243.8 dB.

A New Three-Phase DPLL Frequency Estimator Based on Nonlinear Weighted Mean for Power System Disturbances

A new three-phase digital phase-locked loop (DPLL) is proposed to determine the instantaneous grid frequency under power system disturbances. The proposed solution is based on single-phase DPLL algorithms, defining the estimated grid frequency as a nonlinear weighted mean of the three single-phase DPLL outputs. Orthogonal signals required by the DPLL algorithms are obtained through a fictitious quadrature voltage using five different appropriated approaches. The proposed structures have been assessed through extensive analysis under balanced and unbalanced conditions. For this purpose, real voltage dips collected in a Spanish wind farm along several months are included in the paper as examples of frequency estimations. In addition, results from conventional three-phase DPLL topologies are presented to confirm the validity of the proposed DPLL structures.

Flicker Noise in Observer-Controller Digital PLL

The observer-controller loop filter proposed in the author's prior work is extended to include the effect of flicker noise in the digital-controlled oscillator (DCO). We show that the same implementation structure, as in the author's prior work but with modified gain values to account for the effect of flicker noise, can be used to achieve near-ideal jitter performance. A frequency domain analysis of the observer-controller loop filter is presented to provide a more intuitive understanding of the loop filter operation. The analysis shows that a system zero is introduced at dc to filter out the flicker noise and that the observer-controller based digital phase-locked loop (DPLL) remains effectively a second-order system regardless of the transport delay in the digital feedback loop. A comparison with conventional DPLL loop filter is also provided, which shows that in the presence of flicker noise, the jitter performance is even further improved than in the author's prior work.

Observer-Controller Digital PLL

A digital phase-locked loop (DPLL) has been recently developed to exploit the increasing transistor speed of modern process technology. By employing a digitally controlled oscillator (DCO) and a time-to-digital converter (TDC), the loop filter of a DPLL becomes all-digital. Instead of designing the loop filter by digitizing a continuous-time loop response as has been commonly done, more sophisticated control schemes can be employed. In this paper, we propose to design the feedback loop in the time-domain by first modeling the DCO and TDC as a noisy ?plant? in state-space form. Based on a Kalman observer of the ?plant,? the proposed approach then generates optimal control signals that accurately account for the additive noise as well as the transport delay in the digital feedback system. The proposed observer-controller loop filter achieves rapid transient response time and significantly reduces the steady-state phase noise jitter compared to the conventional DPLL. Furthermore, the proposed approach enables modeling of other noise sources such as due to oscillator pulling, which is a common problem in many modern transceivers. By employing the observer-controller loop filter, the effect of oscillator pulling can be effectively removed without degrading the overall phase noise performance.

A novel flash fast-locking digital phase-locked loop: design and simulations

A flash digital phase-locked loop (DPLL) is designed using 0.18 μm CMOS process and a 3.3 V power supply. It operates in the frequency range 200 MHz-2 GHz. The DPLL operation includes two stages: (i) a novel coarse-tuning stage based on a flash algorithm similar to the algorithm employed in flash A/D converters, and (ii) a fine-tuning stage similar to conventional DPLLs. The flash portion of the DPLL is made up of frequency comparators, an encoder and a decoder which drives a multiple charge pump (CP)/lowpass filter (LPF) combination. Design considerations of the flash DPLL circuit components as well as implementation using Cadence design tools are presented. Spectre simulations were also performed and demonstrated a significant improvement in the lock time of the flash DPLL as compared to the conventional DPLL. By increasing the number of frequency comparators, the lock time is expected to be always less than 100 ns in the above-mentioned frequency range.

Fuzzy two-stage carrier synchronization

This paper presents a novel two-stage carrier synchronization scheme. It provides both faster acquisition and better noise suppression than a conventional digital phase-locked loop (DPLL). The first stage produces the frequency estimate. The second stage is a new phase estimator, a DPLL with fuzzy adaptive bandwidth, to track frequency offset and phase. The simulation results show the improved performance. The main advantage of the proposed scheme over [7] is that it does not need optimization of fuzzy membership functions and a low computational cost of a DPLL is preserved.

High resolution frequency tracking system using the maximum entropy method

Abstract The tracking capability of the maximum entropy method (MEMrpar; is employed to develop a novel digital frequency-locked loop (DFLLrpar;. Unlike the conventional digital phase-locked loop (DPLLrpar;, the proposed DFLL locks directly on the frequency. In addition to the well-known components of the DPLL, the new DFLL includes a low-order MEM frequency estimator. The DFLL is shown to be capable of tracking a wide range of frequencies in servere noisy environments. It is computationally attractive. Simulation results are included.

Symmetric lock-range multilevel quantized digital phase locked FM demodulator

A dynamic modification algorithm of the conventional digital phase-locked loop (CDPLL) design parameters is proposed to get a modified DPLL (MDPLL) which has nearly symmetric two-sided acquisition range. With the help of extensive simulation results, it is established that in comparison to a CDPLL, the MDPLL has larger acquisition range and better FM demodulation capability. The performance degradation due to additive noise is more pronounced in the case of an MDPLL. >

Noise analysis of a digital tanlock loop

The noise performance analysis of a nonuniform digital phase-locked loop (DPLL), called the digital tanlock loop (DTL), is investigated by both analytic and computer-simulation methods. The results are presented in terms of phase error probability mass function and mean time to skip cycle versus input signal-to-noise ratio (SNR). These results are compared to the ones obtained with the conventional sinusoidal DPLL loop (DPLL). It is found that, for low-to-moderate input SNR, the DTL has only a slight improvement over the DPLL. The DTL, however, has larger linear characteristics than the conventional DPLL, which makes it attractive for applications that require an increased tracking range or as a first stage in carrier tracking systems based on optimum estimation procedures such as a Kalman smoother.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Novel quick-response, digital phase-locked loop

The structure of a conventional digital phase-locked loop has been modified to improve its transient response. The superiority of the new loop has been established analytically and by computer simulation results.

Performance Analysis of Digital Tanlock Loop

In this paper, a nonuniform-sampling digital phaselocked loop (DPLL) called the digital tanlock loop (DTL), which uses a new type of phase error detector with linear phase characteristic, is studied. The main feature of the DTL is that the phase error detector, using the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">tan^{-1}(.)</tex> function with in-phase and quadrature samples of the incoming signal, has a linear characteristic with a period of 2π. Accordingly, the DTL can be characterized by a linear difference equation, thereby making it possible to analyze the loop easily, without approximation of nonlinearity as is usually done in analysis of a conventional DPLL with sinusoidal phase characteristic. The performances of the first- and second-order DTL's in the absence and presence of noise have been investigated by analysis and computer simulation. It is shown that the linear phase characteristic results in many attractive features in comparison to the conventional DPLL with the sinusoidal phase characteristic. These include insensitivity of the locking conditions to variation of input signal power, more noise immunity, wider lock range and less steady-state phase error of the first-order loop for an input with frequency offset, and much less sensitivity to initial phase errors in convergence of the second-order loop.

Linear digital phase-locked loops using integrators in a pulse frequency-modulation system

The conventional digital phase-locked loop (DPLL) has a number of problems which need to be solved: the pull-in and lock ranges are very restricted by the phase detector and are dependent on the noise bandwidth, and their operation is not linear. In the paper, DPLLs free from such disadvantages are proposed. These DPLLs are realised by a new method, i.e. by use of integrators in a pulse frequency-modulation system, and the higher-order DPLL is systematically designed by controlling the free-running frequency of one VCO with the error of the other DPLLs. The operation of the DPLL is similar to that of an analogue PLL (APLL). However, the former operates linearly in a wider region than does the latter; unlike the APLL, the pull-in and lock ranges of the first-order and imperfect second-order DPLL are the same as those of the perfect second- order APLL in the range from zero to almost the maximum frequency of the VCO and are independent of the noise bandwidth. Excellent agreement is obtained between theory and experiments.

High‐speed digital PLL using trigger oscillators

AbstractThe conventional digital phase‐locked loop (DPLL) cannot be used for high‐frequency purposes, because the local oscillator frequency of the DPLL is several times the input frequency. This paper proposes a use of trigger oscillators to the DPLL. The first‐ and second‐order DPLL's using trigger oscillators can be used if input frequency is as high as the maximum logic clock frequency. The quantization noises of the second‐order DPLL using two trigger oscillators are lower than those of the conventional DPLL. The trigger oscillators can be used in any type of DPLL. Its input frequency becomes higher or its quantization noises become lower.