Conventional Digital Design Research Articles

An 11.36-Bit 405 μW SAR-VCO ADC with single-path differential VCO-based quantizer in 65 nm CMOS

In this paper, a low-power, small-area SAR-VCO ADC is proposed using a highly linear and single-path differential VCO-based quantizer. Compared to conventional digital solution or analog design, proposed digital synthesizable dynamic voltage comparator (DVC) employs a two-stage structure, which reduces the comparator delay and offset and saves chip area. Furthermore, improved differential voltage-to-current (V–I) converter enables the realization of a single-path differential VCO-based quantizer. Trimming circuits enhance the robustness of VCO, compensating for variations induced by process variations. Additionally, a novel frequency-to-digital converter (FDC) is used as the fine quantization to directly measure the frequency. Finally, a SAR-VCO ADC is realized in 65 nm CMOS process. The simulation results show that the signal-to-noise distortion ratio (SNDR) is 70.16 dB under sampling rate of 7.8 MHz at oversampling rate (OSR) of 8. The proposed ADC has a supply voltage of 1.2V and a power consumption of 405 μW. It occupies an area of 0.16 mm2, and achieves an area figure of merit (FoMA) of 25.12 fJ*mm2/conversion-step.

A Scalable Formal Framework for the Verification and Vulnerability Analysis of Redundancy-Based Error-Resilient Null Convention Logic Asynchronous Circuits

The increasing demand for high-speed, energy-efficient, and miniaturized electronics has led to significant challenges and compromises in the domain of conventional clock-based digital designs, most notably reduced circuit reliability, particularly in mission-critical hardware. At scaled technology nodes, devices are vulnerable to transient or soft errors, such as Single Event Upset (SEU) and Single Event Latch-up (SEL). External radiation, internal electromagnetic interference (EMI), or noise are the primary sources of these errors, which can compromise the circuit functionality. In response to these challenges, the Quasi-Delay-Insensitive (QDI) Null Convention Logic (NCL) asynchronous design paradigm has emerged as a promising alternative, offering advantages such as ultra-low power performance, reduced noise and EMI, and resilience to process, voltage, and temperature variations. Moreover, its unique architecture and insensitivity to timing variations offers a degree of resistance against transient errors; however, it is not entirely resilient. Several resiliency schemes are available to detect and mitigate soft errors in QDI circuits, with approaches based on redundancy proving to be the most effective in ensuring complete resilience across all major QDI implementation paradigms, including NCL, Pre-charge/Weak-charge Half Buffers (PCHB/WCHB), and Sleep Convention Logic (SCL). This research focuses on one such redundancy-based resiliency scheme for QDI NCL circuits, known as the dual-modular redundancy-based NCL (DMR-NCL) architecture, and addresses the absence of formal methods for the verification and analysis of such circuits. A novel methodology has been proposed for formally verifying the correctness of DMR-NCL circuits synthesized from their synchronous counterparts, covering both safety (functional correctness) and liveness (the absence of deadlock). In addition, this research introduces a formal framework for the vulnerability analysis of DMR-NCL circuits against SEU/SEL. To demonstrate the framework’s efficacy and scalability, a prototype computer-aided support tool has been developed, which verifies and analyzes multiple DMR-NCL benchmark circuits of varying sizes and complexities.

A Novel Guided Box Filter Based on Hybrid Optimization for Medical Image Denoising

Medical image denoising is a crucial pre-processing task in the medical field to ensure accurate analysis of anomalies or sicknesses in the human body. Digital filters are popular for reducing undesired noise as they provide reliability, high accuracy, and reduced sensitivity to component tolerances compared to analog filters. However, conventional digital filter design approaches lack efficiency in achieving global optimization robustness. To overcome these incapabilities, this paper adopted bio-inspired optimization algorithms to offer viable digital filter designing tools because of their simple implementation and requirement of a few parameters to control their convergence. This research article explores a hybrid strategy that combines a novel guided decimation box filter (GDBF) with a hybrid cuckoo particle swarm optimization (HCPSO) algorithm to design a denoising filter for medical images. It is the first time a decimation box filter has been used for denoising, leading to novelty. The HCPSO algorithm is applied to obtain the filter parameters optimally. Medical images mostly suffer from four types of noises. The performance of the proposed filter is analyzed for these types of noise. To highlight the importance of parameter selection, the results of the proposed method are compared with other recently utilized bio-inspired genetic algorithms, such as PSO (particle swarm optimization), CS (cuckoo search), and FF (firefly). The superiority (potency) of the proposed method has been established by calculating the improvement in quality parameters such as the peak signal-to-noise ratio (PSNR), structure similarity index (SSIM), and feature similarity index (FSIM). The proposed filter achieved the highest PSNR (~35.7 dB), SSIM (~0.95), and FSIM (~0.92) and proved its numerical and visual quality efficacy over state-of-the-art models.

Bitstream-Based Neural Network for Scalable, Efficient, and Accurate Deep Learning Hardware.

While convolutional neural networks (CNNs) continue to renew state-of-the-art performance across many fields of machine learning, their hardware implementations tend to be very costly and inflexible. Neuromorphic hardware, on the other hand, targets higher efficiency but their inference accuracy lags far behind that of CNNs. To bridge the gap between deep learning and neuromorphic computing, we present bitstream-based neural network, which is both efficient and accurate as well as being flexible in terms of arithmetic precision and hardware size. Our bitstream-based neural network (called SC-CNN) is built on top of CNN but inspired by stochastic computing (SC), which uses bitstreams to represent numbers. Being based on CNN, our SC-CNN can be trained with backpropagation, ensuring very high inference accuracy. At the same time our SC-CNN is deterministic, hence repeatable, and is highly accurate and scalable even to large networks. Our experimental results demonstrate that our SC-CNN is highly accurate up to ImageNet-targeting CNNs, and improves efficiency over conventional digital designs ranging through 50–100% in operations-per-area depending on the CNN and the application scenario, while losing <1% in recognition accuracy. In addition, our SC-CNN implementations can be much more fault-tolerant than conventional digital implementations.

Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks

To enable essential deep learning computation on energy-constrained hardware platforms, including mobile, wearable, and Internet of Things (IoT) devices, a number of digital ASIC designs have presented customized dataflow and enhanced parallelism. However, in conventional digital designs, the biggest bottleneck for energy-efficient deep neural networks (DNNs) has reportedly been the data access and movement. To eliminate the storage access bottleneck, new SRAM macros that support in-memory computing have been recently demonstrated. Several in-SRAM computing works have used the mix of analog and digital circuits to perform XNOR-and-ACcumulate (XAC) operation without row-by-row memory access and can map a subset of DNNs with binary weights and binary activations. In the single array level, large improvement in energy efficiency (e.g., two orders of magnitude improvement) has been reported in computing XAC over digital-only hardware performing the same operation. In this article, by integrating many instances of such in-memory computing SRAM macros with an ensemble of peripheral digital circuits, we architect a new DNN accelerator, titled Vesti . This new accelerator is designed to support configurable multibit activations and large-scale DNNs seamlessly while substantially improving the chip-level energy-efficiency with favorable accuracy tradeoff compared to conventional digital ASIC. Vesti also employs double-buffering with two groups of in-memory computing SRAMs, effectively hiding the row-by-row write latencies of in-memory computing SRAMs. The Vesti accelerator is fully designed and laid out in 65-nm CMOS, demonstrating ultralow energy consumption of $ for CIFAR-10 classification at 1.0-V supply.

A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage-Scalable Design

In order to fulfill different demands between ultralow energy consumption and high performance, integrated circuits are being designed to operate across a large range of supply voltages, in which resiliency to timing violation is the key requirement. Unfortunately, traditional timing analysis which focuses on setup timing tolerance for higher performance cannot model the hold violation efficiently across different voltages. In this paper, we proposed a complete flow of computationally efficient methodology for guaranteeing hold margin, which is particularly important for low-power devices, e.g., Internet-of-Things devices. Leveraging both the conventional static timing analysis and a most probable point (MPP) theory, we develop a new hold-timing closure methodology across voltages eliminating expensive Monte Carlo simulation. To improve the efficiency of locating MPP, a novel MPP search method is proposed that employs a set of approximation eliminating the time-consuming iterative search. Several novel modeling techniques, such as the incorporation of nonlinear behaviors of circuit operations and correlation coefficient modeling, are also proposed in this paper to significantly improve the accuracy of the design. With the proposed modeling techniques, a novel hold resilient design technique equipped with the proposed variation-aware timing resilient flip-flop is developed. The proposed design technique eliminates the excessive hold-fixing operation at low voltage and its associated performance degradation at high voltage, whereas still being compatible with the conventional design closure flow. Design example on a voltage-scalable digital signal processor was used to demonstrate the potential of the technique. The result in a 45-nm technology shows that the elimination of more than 20 000 hold buffers, 23% performance improvement at high voltages, and 7% area saving are achieved using the proposed technique compared with the conventional digital design technique.

A Novel Heterogeneous Approximate Multiplier for Low Power and High Performance

Approximate computing is a design paradigm considered for a range of applications that can tolerate some loss of accuracy. In fact, the bottleneck in conventional digital design techniques can be eliminated to achieve higher performance and energy efficiency by compromising accuracy. In this letter, a new architecture that engages accuracy as a design parameter is presented, where an approximate parallel multiplier using heterogeneous blocks is implemented. Based on design space exploration, we demonstrate that introducing diverse building blocks to implement the multiplier rather than cloning one building block achieves higher precision results. We show experimental results in terms of precision, delay, and power dissipation as metrics and compare with three previous approximate designs. Our results show that the proposed heterogeneous multiplier achieves more precise outputs than the tested circuits while improving performance and power tradeoffs.

A Novel Integrated Circuit Design Methodology Using Dynamic Library Concept with Reduced Non-Recurring Engineering Cost and Time-to-Market

The Incremental and iterative steps in the conventional digital IC design and automation flow increase the design time and non-recurring engineering cost (NRE), which are the two major driving factors of the IC industry. Reducing both at the same time is a challenge to the research community to come up with a design automation solution. In this paper, we propose a novel and unified methodology by merging the frontend and backend stages of the IC design process which eliminates the frontend CAD tool usage to minimize the Design time and NRE cost. Moreover, the complexity of hierarchical design steps is drastically reduced by mapping the input register-transfer level (RTL) description directly to their corresponding physical designs, derived using the existing CAD tools and stored in pre-computed technology libraries. We introduce the Dynamic Libraries, which store the layouts of the already designed blocks and their references for the later use in further designs. We further validated our methodology with 32-bit ALU which has its vital appearance in all the processors and controllers. The mapping techniques are validated on industrial standard benchmark circuits. These validations witness the considerable improvements in design time over the conventional design methodologies.

Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator

This paper presents a dual-loop ADPLL suitable for video pixel clock generation. The dual-loop architecture where a fast subloop works as a DCO inside a main loop is chosen since it can efficiently suppress the ring oscillator phase noise. In order to satisfy a wide tuning range and fine resolution requirements in the pixel clock PLL, the TDC and DCO with two-step and bottom-up control are employed. An s-domain model is utilized to tune the loop parameters so that the dual-loop PLL has the optimum jitter performance. The measurement results match well with the proposed s-domain model and clearly show the effectiveness of the dual loop in suppressing the phase noise of the DCO. We propose a new cell-based layout technique to avoid performance degradation during automatic placement and routing, which is compatible with the conventional digital design environment. A chip that occupies 0.032 mm2 has been fabricated in the 28-nm CMOS technology. The synthesized DCO shows 1.7-LSB DNL which is close to a full-custom layout. The rms integrated jitter is only 15 ps at 250 MHz, even though PLL operates at the extremely low input frequency of 100 kHz. Power consumption is 3.1 mW at 250 MHz with a 1.0-V supply.

A CNN-Specific Integrated Processor

Integrated Processors (IP) are algorithm-specific cores that either by programming or by configuration can be re-used within many microelectronic systems. This paper looks at Cellular Neural Networks (CNN) to become realized as IP. First current digital implementations are reviewed, and the memoryprocessor bandwidth issues are analyzed. Then a generic view is taken on the structure of the network, and a new intra-communication protocol based on rotating wheels is proposed. It is shown that this provides for guaranteed high-performance with a minimal network interface. The resulting node is small and supports multi-level CNNdesigns, giving the systema 30-fold increase in capacity compared to classical designs. As it facilitates multiple operations on a single image, and single operations on multiple images, with minimal access to the external image memory, balancing the internal and external data transfer requirements optimizes the system operation. In conventional digital CNN designs, the treatment of boundary nodes requires additional logic to handle the CNN value propagation scheme. In the new architecture, only a slight modification of the existing cells is necessary to model the boundary effect. A typical prototype for visual pattern recognition will house 4096 CNN cells with a 2% overhead for making it an IP.

Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip

Clock distribution is an important issue when designing multi processor systems-on-chip on deep sub-micron technology nodes and non-synchronous approaches are becoming popular in this field. This work presents a low-complexity link microarchitecture for mesochronous on-chip communication that enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. With respect to the state of the art, the proposed link architecture stands for its low power and low complexity overheads; moreover it can be easily integrated in a conventional digital design flow since it is implemented by means of standard cells only. Results are presented referring to the link integrated within a multi processor tiled architecture based on a network-on-chip communication backbone on a CMOS 65 nm technology.

An Analysis of Internal Parameter Variations Effects on Nanoscaled Gates

The predicted deterioration of the component quality, due to the shrinking of components to near atomic scale, threatens the effectiveness and the applicability of conventional digital system design methodologies in the giga and tera-scale integration era. Three aggression sources support the previous statement: i) the increasing device parameter variability induced by the extreme reduction of the critical feature sizes and the intrinsic nature of new devices; ii) the intense and practically unpredictable internal noise; and iii) the large number of physical defects. This paper provides a detailed analysis of the noise and parameter variations effects on a basic processing gate. We derive formulas to calculate the expected value and the variance of the gate output under the effects of noise, threshold, and gain fluctuations. Using these expressions we also derive a cost-performance equation that evaluates the gate error probability from its parameter variability, noise, power, and area or redundance. The proposed model is generic for any computing gate in the current digital paradigm. To illustrate the model applicability we calculate the error probability curve for a 90 nm CMOS inverter showing that for this technology the noise is the main limiting factor. A tradeoff analysis of area-power-redundancy-reliability for nanogates is performed indicating that the use of nanoscale individual elements for fabricating gates in deep-nanoscale technologies may not be a viable option. The results clearly suggest that the use of redundant structures is necessary and that averaging structures with mid-high redundancy factors may constitute a reasonable solution for building reliable nanoscale gates.

Photonic Microwave Filter With Negative Coefficients Based on WDM Techniques

A novel photonic microwave filter based on multiple optical carriers and a dispersive medium which allows the implementation of filters with negative coefficients is proposed and experimentally demonstrated. Negative coefficients are obtained using a differential detection scheme. The architecture allows the synthesis of photonic microwave filters using conventional digital filter design procedures and using mass-market optical devices.

New design procedure for digital filters based on a finite-state machine implementation

The concept of a finite-state machine (FSM) is used in an attempt to cover the deficiencies of the conventional digital filter design procedure with respect to finite-word-length effects. The problem of synthesis is considered in detail and a procedure whereby the FSM mappings are designed to best model a given difference equation is presented. This procedure is based on a well known graph theory algorithm. The FSM digital filter design procedure is evaluated by computer simulation of various small-word-length filters. Several examples are presented to demonstrate the improved performance of the FSM filters with respect to conventional fixed-point designs. The design procedure also allows the construction of limit-cycle-free high-order direct-form filters. This form is compared to the more conventional cascade structure.

A Microcomputer Training Course

A major effort to upgrade training programs to include microcomputer concepts is becoming necessary in many government, industrial and educational institutions. Professional and technical staff who are familiar with conventional digital logic design need to learn new techniques and new technical jargon. This paper will describe training objectives which must be kept in mind when designing or evaluating microprocessor courses. These objectives include giving the student a detailed understanding of the operation of all elements in the basic CPU-memory-I/O microprocessor system configuration. The relationship between the hardware operation and the instruction set of the machine must be emphasized, and machine level programming must be understood. Laboratory exercises are suggested.

Developing Programmable Broad-Band Counting Circuits for High-Speed Data Transmission and Frequency Division

Through the advancement of integrated-circuit (IC) technology new approaches for programmable counting circuits are made feasible. Frequencies up to 1.2 GHz are programmable divided by a new breed of MSI-counters for ultra-high-frequency communications systems. After reviewing, the already known speed enhancing techniques, a new counting method (the patents of which is pending) is introduced to allow higher counting speeds. By using a shift register and some gates, applications at frequencies up to the gigahertz region, one to two orders of magnitude higher than conventional programmable counting, are made possible. The programmable counters developed use the new technique to eliminate the set-up time constraint of the IC employed. This boosts the counting frequency up to maximum toggle frequency of the IC. The method described is ideally suited for phase-locked loop (PLL) synthesizers for at least two reasons. First, it eliminates much of the prescaling required by slower counters. Second, it allows, in opposition to pulse-swallowing techniques, low-division ratios, and improved PLL performance. The simplicity of the method and the low package count make it suitable for MSI and LSI. This paper discusses the design approach used to implement programmable digital counters, for applications in nowadays fastest digital systems, utilizing currently available IC's. With more and more versatility being offered by IC's a fresh look is in order at conventional digital counter design. Decimal counter sections are available in IC-form usually with four stages to a package. Their use can afford considerable savings in space interconnections and power consumption.

Digital encoding and filtering using delta modulation

Digital filters are described which are based on delta modulation rather than pulse code modulation. It is shown that delta modulation encoding may be combined with digital filtering to realize either nonrecursive or recursive types. Conventional digital filter design techniques are applicable in both cases. Simulation of such filters on a small computer is discussed. Quantization noise is considered and comparisons made with the noise performance of the conventional digital filter.