Conventional Delay-locked Loop Research Articles

A general jitter analysis of DLL considering the jitter accumulation effect of loop capacitor

This paper presents a time-domain model for general jitter analysis of delay-locked loops (DLLs). According to this model, the noise contribution of each part of the circuit is specified at the output of DLL, and a closed-form relationship is extracted. By this closed-form relationship, we show that accumulated jitter, known as jitter peaking, always exists due to the loop filter capacitor in a widely used DLL configuration. The effect of jitter accumulation can cause an unstable lock state. A conventional DLL is simulated in 0.18 µm CMOS technology to verify the closed-form relationship.

Auto-Zeroing Static Phase Offset in DLLs Using a Digitally Programmable Sensing Circuit

This brief presents a static phase offset (SPO) reduction technique through auto-zeroing in a delay-locked loop (DLL). We propose a self-calibrated, digitally programmable, sensing circuit that can measure both the polarity and the magnitude of the SPO. The SPO is suppressed by tuning a pair of digital-to-time converters (DTCs) at the input of the phase frequency detector (PFD). The proposed technique enables run-time background calibration and can suppress the SPO caused by artifacts from the PFD, charge pump, and loop filter capacitor. Monte Carlo simulation results show that the SPO in a conventional DLL implementation improves from 12.92 ps to 0.90 ps when the proposed auto-zeroing technique is employed.

A subspace-based code tracking loop design for GPS multi-antenna receiver in multipath environment

Global Navigation Satellites Systems have been greatly developed in recent years, but receivers usually suffer the undesired measurement bias errors caused by multipath incidence in an urban area. We propose an effective subspace-based estimator cooperating with the conventional delay-locked loop (DLL) for Global Positioning System L1 C/A Signal. With the help of the multi-antenna, the incident rays could be distinguished in space. A forward and backward space spatial smooth technique is then taken to solve the coherent problem in signal subspace estimation. By using the structure of the receiving array, a subspace rotation invariance can be built, and the angles of arrival and relative delays of incident rays could be estimated jointly. After combining the estimates from DLL and subspace-based estimators, we can enhance the strength of the line-of-sight ray and achieve a modified delay tracking output without multipath bias effectively. Simulation results prove that compared with the existing methods, such as the narrow early-minus-late and the multipath estimating delay lock loop, the proposed method has the best multipath mitigation in the delay estimation.

Multipath Estimating Delay Lock Loop for LTE Signal TOA Estimation in Indoor and Urban Environments

Long-term evolution (LTE) signals are potential signals-of-opportunity for position and navigation, especially in challenging urban and indoor environments. A major challenge is that the LTE signal time-of-arrival (TOA) estimations are susceptible to the multipath propagation effects. In this paper, the multipath estimating delay lock loop (MEDLL), which is originally designed for global positioning system receivers, is applied to LTE signal TOA estimation in multipath environments. We derive the analytical expression of the correlation function for LTE signals and present the procedure for estimating parameters of the detected multipath components. Two initialization methods without and with super-resolution algorithm (SRA) are developed for the MEDLL. Our analyses show that the MEDLL with SRA-based initialization can achieve better multipath resolution, while the one without SRA has less complexity. Extensive simulations involving static multipath scenarios are conducted to examine the statistical TOA estimation performance of the proposed MEDLL with LTE cell-specific reference signal. The simulation results and computational complexity analysis indicate that the proposed MEDLL outperforms the conventional delay lock loop and SRA in term of multipath mitigation performance and computational complexity. Experimental results using real collected LTE signals in urban environments are also provided to demonstrate the effectiveness of the proposed technique for realistic scenarios.

Low Settling Time All Digital DLL for VHF Application

Settling time is one of the most important parameter in design of DLLs. In this paper we propose a new high speed with low settling time Delay Locked Loop (DLL) in which a digital signal processor (DSP) is used instead of using phase-frequency detector, charge pump and loop filter in conventional DLL. To have better settling time, PRP conjugate gradient algorithm is used to optimize delay of each delay cells. Since this novel architecture has removed phase detector, charge pump and loop filter, the proposed structure shown occupy smaller chip area and has less settling time than conventional DLLs. This method could be implemented in a real system by means a digital signal processor device. Simulation has been done for 15 delay cells and fREF is chosen 14MHz to have output frequency 14×15=210MHz. fOUT=210 MHz is one of the channels in Iran VHF frequency band. As shown with simulations, the proposed architecture has locking time approximately 286nsec which is equal to 4 clock cycles of reference clock.

A Noise and Mismatches of Delay Cells and Their Effects on DLLs

Jitter is one of the most important parameters in design of delay locked loop (DLL) based frequency synthesizer. In this paper noise and mismatches of conventional delay cells which are mainly used in the DLLs architecture are introduced completely. First, time domain equations related to noise and mismatches of conventional delay cells are reported. Then, these equations are used to calculate jitter of DLL due to mismatch and noise of delay cells. At last closed form equations are obtained which can be used in the designing of low jitter DLLs. To validate these equations, a conventional DLL is designed in TSMC 0.18um CMOS Technology.

A 125MHz 64-Phase Delay-Locked Loop with Coarse-Locking Circuit Independent of Duty Cycle

A 125MHz 64-phase delay-locked loop (DLL) is implemented for time recovery in a digital wire-line system. The architecture of the proposed DLL comprises a coarse-locking circuit added to a conventional DLL circuit, which consists of a delay line including a bias circuit, phase detector, charge pump, and loop filter. The proposed coarse-locking circuit reduces the locking time of the DLL and prevents harmonic locking, regardless of the duty cycle of the clock. In order to verify the performance of the proposed coarse-locking circuit, a 64-phase DLL with an operating frequency range of 40 to 200MHz is fabricated using a 0.18-µm 1-poly 6-metal CMOS process with a 1.8V supply. The measured rms and peak-to-peak jitter of the output clock are 3.07ps and 21.1ps, respectively. The DNL and INL of the 64-phase output clock are measured to be -0.338/+0.164 LSB and -0.464/+0.171 LSB, respectively, at an operating frequency of 125MHz. The area and power consumption of the implemented DLL are 0.3mm2 and 12.7mW, respectively.

A new fast‐lock, low‐jitter, and all‐digital frequency synthesizer for DVB‐T receivers

SummaryLock time and convergence time are the most important challenges in delay‐locked loops (DLLs). In this paper we cover French very high frequency band with a novel all‐digital fast‐lock DLL‐based frequency synthesizer. Because this new architecture uses a digital signal processing unit instead of using phase frequency detector, charge pump, and loop filter in conventional DLL, therefore, it shows better jitter performance, lock time, and convergence speed than previous related works. Optimization methods are used to make input and output signals of the proposed DLL in phase. The proposed architecture is designed to cover all channels of French very high frequency band by choosing number of delay cells in signal path. Simulation has been done for 22–27 delay cells, and fREF = 16 MHz, which can produce output frequency in range of 176–216 MHz. Locking time is approximately 0.3 µs, which is equal to five clock cycles of reference clock. All of the simulation results show superiority of the proposed structure. Copyright © 2013 John Wiley & Sons, Ltd.

All digital fast lock DLL-based frequency multiplier

One of the most important parameters in the design of synthesizers is lock time. A new fast lock delay locked loop (DLL) based frequency multiplier is proposed in this paper. Phase detector, charge pump and loop filter in conventional DLLs are replaced by a digital signal processor in the proposed structure. This leads to have better lock time, higher speed and smaller chip aria. The proposed structure can be implemented easily in a real system by means of a suitable powerful digital signal processor. Simulation has been done for 11 delay cells as a delay chain and input frequency equal with 300 MHz. The output frequency is multiplied by 11 (fOUT = 3.3 GHz), and lock time is obtained about 13 ns which is equal to 4 clock cycles of reference clock.

A low power DLL based clock and data recovery circuit with wide range anti-harmonic lock

This paper presents a wide frequency range CDR circuit for second generation AiPi+ intra-panel interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with conventional AiPi+. The DLL-based CDR architecture is adopted to generate multi-phase clocks. We propose a simple scheme for a frequency detector (FD) to overcome the limited frequency range and false lock problem of a conventional delay-locked loop (DLL) to reduce the complexity. In addition, a duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatches between rising and falling time of delay cells in the VCDL. Also, the proposed simple DLL architecture comprised of frequency and phase detectors has better process-portability. The proposed CDR is implemented in 0.18 μm technology and the active die area is 660 × 250 μm. The implemented DLL covers a frequency range from 62 to 128 MHz, which is limited only by the characteristics of the delay cell. The peak-to-peak jitter is less than 13 ps when the input frequency is 128 MHz, and the power consumption of the CDR except the input buffer, equalizer, and de-serializer is 5.94 mW from the supply voltage of 1.8 V.

Jitter Analysis of Polyphase Filter-Based Multiphase Clock in Frequency Multiplier

This paper presents the random jitter and deterministic jitter analysis on the proposed polyphase filter (PPF)-based multiphase clock in frequency multiplier with reference to the benchmark jitter analysis of the multiphase clock counterpart using conventional delay-locked loop (DLL) approach. The analysis results have shown that the jitter performance of PPF-based design is better than that of DLL-based design. Jitter measurement on the PPF-based multiphase clock chip has been conducted. The overall comparison has shown excellent agreement among prediction results from theory and realistic simulation results from a combination of all the transistor-level circuits in conjunction with the proposed behavioral model. The comparison results confirm the proposed time domain jitter analysis method. The results have shown that not only do the PPF-based demonstrate the improved jitter performance, the deterministic jitter performance is also independent of components mismatch. Finally, the practical measurement results of the fabricated chip identifies the practical pitfalls of the proposed PPF-based DLL design, suggesting further jitter reduction and demonstrating the potential low-jitter design using the PPF-based DLL.

A low-complexity adaptive receiver for DS-CDMA systems in unknown code delay environment

In direct-sequence code division multiple access (DS/CDMA) multiuser communication systems in multipath channels, both intersymbol interference (ISI) and multiple-access interference (MAI) must be considered. The multipath channel characterizes the propagation effects including the timing offset and delays, etc. Traditionally, we use the delay-locked loop (DLL) code tracking loop to recover the timing delay. But DLL cannot work well in multipath environment. In this paper, we propose a low-complexity adaptive receiver to suppress ISI/MAI and solve the timing offset problems without using conventional DLL code tracking loop. The proposed receiver employs an adaptive filter whose weights are adapted using a block least-mean square error algorithm with fractional sampling. Simulations confirm the good performance, including learning curves and theoretical analysis of minimum mean-square error, of the proposed receiver. Copyright © 2010 John Wiley & Sons, Ltd.

A 90° phase-shift DLL with closed-loop DCC for high-speed mobile DRAM interface

In this paper, a 90° phase-shift delay-locked loop (DLL) with closed-loop duty-cycle correction (DCC) is proposed. The proposed DLL increases the accuracies of the duty cycle and 90° phase shift by compensating PVT variation using a closed-loop DCC and a closed-loop 90° phase shift, and achieves a smaller area by reducing the delay-line length by 25% to 50% as compared to conventional DLLs with the DCC and/or 90° phase shift. We also propose a 90° phase detector consisting of a time-to-voltage converter and a sense amplifier to independently control and lock the DCC and 90° phase-shift loops. The proposed DLL is designed using the 0.13 μm process technology with a 1.2 V supply voltage. The operating frequency range is from 400 MHz to 800 MHz. Monte Carlo simulation results show that the output duty cycle error ranges from -0.21% to 0.22% for an input duty cycle range of 30% to 70%, and the 90° phase-shift error is less than 1.66°, which is lower than a 5.7ps error at 800 MHz. Finally, the power consumption of the proposed DLL is 2.8 mW at 800 MHz.

An Antiharmonic, Programmable, DLL-Based Frequency Multiplier for Dynamic Frequency Scaling

This paper describes a new delay-locked loop (DLL)-based frequency multiplier, which includes a lock controller and a phase detector to solve the false lock problem and overcome the limited locking range of conventional DLLs. By using the multiple clock phases of the DLL, the lock controller is able to indicate whether the delay time of the VCDL is within the correct locking range or not. A differentially controlled edge combiner is also proposed for the frequency multiplication. The antiharmonic DLL-based frequency multiplier, implemented in a 0.18-μ.m CMOS process, occupies an active area of 0.043 mm2, and dissipates 36.7 mW at 1.7 GHz. The measured root mean square jitter and peak-to-peak jitter for the multiplied output clock at 1.7 GHz are 2.64 and 16.8 ps, respectively.

Analysis on the positioning precision of CAPS

As a newly developed satellite positioning system, the Chinese Area Positioning System (CAPS) is a typical direct sequence spread spectrum ranging system like GPS. The positioning precision of such navigation signals depends on many factors, including the pseudo-code rate, the signal to noise ratio, the processing methods for tracking loops and so on. This paper describes the CAPS link budget, the solution approach for CAPS positioning, focusing on the autocorrelation function feature of C/A code signals. The CAPS signal measurement precision is studied by the software approach together with theoretical analysis of the range resolution. Because the conventional Delay Lock Loop (DLL) is vulnerable to the impact of noise, a narrow correlator and multiple correlators as well as the corresponding discrimination methods of phases are proposed, which improves the robustness of DLL and the code-phase resolution of the measurement. The results show that the improvement of the DLL structure and the discrimination method are the most important way to improve the ranging resolution. Theoretical analysis and experimental results show that a CAPS receiver could reach a 20-m positioning precision by using three satellites with a supported height from an altimeter.

An Infinite Phase Shift Delay-Locked Loop With Voltage-Controlled Sawtooth Delay Line

A wide-range delay-locked loop (DLL) with infinite phase shift and duty cycle control is presented. A voltage-controlled sawtooth delay line provides not only the delay control but also duty cycle control. The proposed DLL achieves infinite phase shift by using a single loop. Therefore, it has the benefits of good jitter and wide range compared with the conventional dual-loop DLL. The proposed DLL has been fabricated in a 0.18-mum CMOS process and the core area is 0.45 times 0.3 mm2. The measurement results show the proposed DLL operates from 50 MHz to 500 MHz. The duty cycle of the output clock can be adjusted from 30% to 60% in the step of 5%. At 500 MHz, the measured peak-to-peak jitter is 11.1 ps and the power consumption is 6 mW.

Improved Delay-Locked Loop in a UWB Impulse Radio Time-Hopping Spread-Spectrum System

As ultra-wideband impulse radio (UWB-IR) uses short-duration impulse signals of nanoseconds, even a small number of timing errors can cause a detrimental effect on system performance. A delay-locked loop (DLL) is proposed to synchronize and reduce timing errors. The design of the DLL is vital for UWB systems. In this paper, an improved DLL is introduced to a UWB-IR time-hopping spread-spectrum system. Instead of using only two central correlator branches as in a conventional DLL, the proposed system uses two additional correlator branches with different delay parameters and different weight parameters. The performance of the proposed schemes with the optimal parameters is compared with that of traditional schemes through simulation: the proposed four-branch DLLs achieves less tracking jitter or a longer mean time to lose lock (MTLL) than the conventional two-branch DLLs if proper parameters are chosen.

A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency-Range Selector for Multiphase Clock Generator

This brief describes a fast-lock mixed-mode delay-locked loop (DLL) for wide-range operation and multiphase outputs. The architecture of the proposed DLL uses the mixed-mode time-to-digital-converter scheme for a frequency-range selector and a coarse tune circuit to reduce the lock time. A multi-controlled delay cell for the voltage-controlled delay line is applied to provide the wide operating frequency range and low-jitter performance. The charge pump circuit is implemented using a digital control scheme to achieve adaptive bandwidth. The chip is fabricated in a 0.25-mum standard CMOS process with a 2.5-V power-supply voltage. The measurements show that this DLL can be operated correctly when the input clock frequency is changed from 32 to 320 MHz, and can generate ten-phase clocks within a single cycle without the false locking problem associated with conventional DLLs and wide-range operation. At 200 MHz, the measured rms random jitter and peak-to-peak deterministic jitter are 4.44 and 15 ps, respectively. Moreover, the lock time is less than 22 clock cycles. This DLL occupies less area (0.07 mm2) and dissipates less power (15 mW) than other wide-range DLLs.

Improvement of jitter transfer characteristics of a 9.95328 Gb/s data recovery DLL using saw filter

This paper presents a design of a high-speed data recovery circuit for non return zero (NRZ) data transmission using delay-locked loop (DLL) with SAW filter. The jitter generation of the circuit is decreased by adjusting the loop gain in DLL whereas surface acoustic wave (SAW) filter with low centered frequency ( f c) improves the jitter transfer function of DLL. It is seen that the circuit using SAW filter of f c = 1.24416 GHz and Q = 1000 provides the cut off frequency of about 600 kHz which is ∼10 times lower than that of conventional DLL circuit.

A Wide Frequency Range Delay-Locked Loop Using Multi-Phase Frequency Detection Technique

This paper presents a wide frequency range delay-locked loop implemented with a 0.35 μm CMOS technology, which can overcome the limited frequency range and false lock problem of conventional delay-locked loop (DLL). The proposed simple DLL architecture comprising frequency and phase detector has better process-portability. The implemented DLL covers frequency range from 10 MHz to 200MHz, which is limited only by the characteristics of delay cell. The DLL consumes 19.8 mW and shows 13 ps rms jitter at 3.3 V, 150 MHz condition.