Conventional Computer Architectures Research Articles

Ferroelectric artificial synapses for high-performance neuromorphic computing: Status, prospects, and challenges

Neuromorphic computing provides alternative hardware architectures with high computational efficiencies and low energy consumption by simulating the working principles of the brain with artificial neurons and synapses as building blocks. This process helps overcome the insurmountable speed barrier and high power consumption from conventional von Neumann computer architectures. Among the emerging neuromorphic electronic devices, ferroelectric-based artificial synapses have attracted extensive interest for their good controllability, deterministic resistance switching, large output signal dynamic range, and excellent retention. This Perspective briefly reviews the recent progress of two- and three-terminal ferroelectric artificial synapses represented by ferroelectric tunnel junctions and ferroelectric field effect transistors, respectively. The structure and operational mechanism of the devices are described, and existing issues inhibiting high-performance synaptic devices and corresponding solutions are discussed, including the linearity and symmetry of synaptic weight updates, power consumption, and device miniaturization. Functions required for advanced neuromorphic systems, such as multimodal and multi-timescale synaptic plasticity, are also summarized. Finally, the remaining challenges in ferroelectric synapses and possible countermeasures are outlined.

Synaptic behavior of Fe3O4-based artificial synapse by electrolyte gating for neuromorphic computing

Neuromorphic computing (NC) is a crucial step toward realizing power-efficient artificial intelligence systems. Hardware implementation of NC is expected to overcome the challenges associated with the conventional von Neumann computer architecture. Synaptic devices that can emulate the rich functionalities of biological synapses are emerging. Out of several approaches, electrolyte-gated synaptic transistors have attracted enormous scientific interest owing to their similar working mechanism. Here, we report a three-terminal electrolyte-gated synaptic transistor based on Fe3O4 thin films, a half-metallic spinel ferrite. We have realized gate-controllable multilevel, non-volatile, and rewritable states for analog computing. Furthermore, we have emulated essential synaptic functions by applying electrical stimulus to the gate terminal of the synaptic device. This work provides a new candidate and a platform for spinel ferrite-based devices for future NC applications.

Experimental Demonstration of Coupled Sub-Harmonic Injection Locked Oscillation in Micro-Electro-Mechanical Relays

The voltage dependence of DC-driven self-sustaining oscillation behavior of a micro-electro-mechanical (MEM) relay makes it possible to influence the phase of oscillation by coupling the gate or body, source and/or drain electrodes to other voltage signals. In this work, sub-harmonic injection locking and synchronized oscillation of electrically coupled MEM relays are experimentally demonstrated, representing a significant milestone toward achieving a MEM-oscillator-based Ising machine that can solve combinatorial optimization problems much more efficiently than conventional computer architectures.

Routing brain traffic through the von Neumann bottleneck: Efficient cache usage in spiking neural network simulation code on general purpose computers

Simulation is a third pillar next to experiment and theory in the study of complex dynamic systems such as biological neural networks. Contemporary brain-scale networks correspond to directed random graphs of a few million nodes, each with an in-degree and out-degree of several thousands of edges, where nodes and edges correspond to the fundamental biological units, neurons and synapses, respectively. The activity in neuronal networks is also sparse. Each neuron occasionally transmits a brief signal, called spike, via its outgoing synapses to the corresponding target neurons. In distributed computing these targets are scattered across thousands of parallel processes. The spatial and temporal sparsity represents an inherent bottleneck for simulations on conventional computers: irregular memory-access patterns cause poor cache utilization. Using an established neuronal network simulation code as a reference implementation, we investigate how common techniques to recover cache performance such as software-induced prefetching and software pipelining can benefit a real-world application. The algorithmic changes reduce simulation time by up to 50%. The study exemplifies that many-core systems assigned with an intrinsically parallel computational problem can alleviate the von Neumann bottleneck of conventional computer architectures.

Complicated Dynamics of a Delayed Photonic Reservoir Computing System

In this paper, we consider the complicated dynamics of a delay-based photonic reservoir computing system. Since conventional computer architectures are approaching their limit, it is imperative to find new, efficient and fast ways of data processing. Photonic reservoir computing (RC) is a promising way which combines the computational capabilities of recurrent neural networks with high processing speed and energy efficiency of photonics. As the RC system is very promising, we analyze its dynamics so that we can make better use of it. In this paper, we mainly focus on its double Hopf bifurcation. We first analyze the existence of double Hopf bifurcation points. Then we use DDE-BIFTOOL to draw the bifurcation diagrams with respect to two bifurcation parameters, i.e. feedback strength [Formula: see text] and delay [Formula: see text], and give a clear picture of the double Hopf bifurcation points of the system. These figures show stability switches and the existence of double Hopf bifurcation points. Finally, we employ the method of multiple scales to obtain their normal forms, use the method of normal form to unfold and classify their local dynamics. The classification and unfolding of these double Hopf bifurcation points are obtained. Three types of double Hopf bifurcations are found. We verify the results by numerical simulations and find its complicated behavioral dynamics. For example, there exist stable equilibrium, stable periodic and quasi-periodic solutions in distinct regions. The discovered rich dynamical phenomena can help us to choose suitable values of parameters to achieve excellent performance of RC.

Decision Support System in a Memristor-Based Mobile CIM Architecture Applied on Big Data Computation and Storage

Data computation and storage are essential parts of developing big data applications. The memristor device technology could remove the speed and energy efficiency bottleneck in the existing data processing. The present experimental work investigates the decision support system in a new architecture, computation-in-memory (CIM) architecture, which can be utilized to store and process big data in the same physical location at a faster rate. The decision support system is used for data computation and storage, with the aims of helping memory units read, write, and erase data and supporting their decisions under big data communication ambiguities. Data communication is realized within the crossbar by the support of peripheral controller blocks. The feasibility of the CIM architecture, adaptive read, write, and erase methods, and memory accuracy were investigated. The integrated circuit emphasis (SPICE) simulation results show that the proposed CIM architecture has the potential of improving the computing efficiency, energy consumption, and performance area by at least two orders of magnitude. CIM architecture may be used to mitigate big data processing limits caused by the conventional computer architecture and complementary metal-oxide-semiconductor (CMOS) transistor process technologies.

Neuromorphic computation with a single magnetic domain wall

Machine learning techniques are commonly used to model complex relationships but implementations on digital hardware are relatively inefficient due to poor matching between conventional computer architectures and the structures of the algorithms they are required to simulate. Neuromorphic devices, and in particular reservoir computing architectures, utilize the inherent properties of physical systems to implement machine learning algorithms and so have the potential to be much more efficient. In this work, we demonstrate that the dynamics of individual domain walls in magnetic nanowires are suitable for implementing the reservoir computing paradigm in hardware. We modelled the dynamics of a domain wall placed between two anti-notches in a nickel nanowire using both a 1D collective coordinates model and micromagnetic simulations. When driven by an oscillating magnetic field, the domain exhibits non-linear dynamics within the potential well created by the anti-notches that are analogous to those of the Duffing oscillator. We exploit the domain wall dynamics for reservoir computing by modulating the amplitude of the applied magnetic field to inject time-multiplexed input signals into the reservoir, and show how this allows us to perform machine learning tasks including: the classification of (1) sine and square waves; (2) spoken digits; and (3) non-temporal 2D toy data and hand written digits. Our work lays the foundation for the creation of nanoscale neuromorphic devices in which individual magnetic domain walls are used to perform complex data analysis tasks.

Robust high-dimensional memory-augmented neural networks

Traditional neural networks require enormous amounts of data to build their complex mappings during a slow training procedure that hinders their abilities for relearning and adapting to new data. Memory-augmented neural networks enhance neural networks with an explicit memory to overcome these issues. Access to this explicit memory, however, occurs via soft read and write operations involving every individual memory entry, resulting in a bottleneck when implemented using the conventional von Neumann computer architecture. To overcome this bottleneck, we propose a robust architecture that employs a computational memory unit as the explicit memory performing analog in-memory computation on high-dimensional (HD) vectors, while closely matching 32-bit software-equivalent accuracy. This is achieved by a content-based attention mechanism that represents unrelated items in the computational memory with uncorrelated HD vectors, whose real-valued components can be readily approximated by binary, or bipolar components. Experimental results demonstrate the efficacy of our approach on few-shot image classification tasks on the Omniglot dataset using more than 256,000 phase-change memory devices. Our approach effectively merges the richness of deep neural network representations with HD computing that paves the way for robust vector-symbolic manipulations applicable in reasoning, fusion, and compression.

Built-in Security Computer: Deploying Security-First Architecture Using Active Security Processor

Continually disclosed vulnerabilities reveal that traditional computer architecture lacks the consideration of security. This article proposes a security-first architecture, with an Active Security Processor (ASP) integrated to conventional computer architectures. To reduce the attack surface of ASP and improve the security of the whole system, the ASP is physically isolated from Computation Processor Units (CPU) with an asymmetric address space, which enables both ASP and CPU to run their operating system and applications independently in their own memory space. Furthermore, the ASP, which has the highest privilege (Super Root) of the whole system, possesses two advantageous features. First, the ASP can efficiently access all CPU resources and collect multi-dimensional information to monitor malicious behaviors, meanwhile, the CPU cannot access the ASP's private resources in any way. Second, instead of being scheduled by CPUs, the ASP can actively manage the security mechanisms employed in either CPUs or the ASP. Based on the security-first architecture, we introduce several typical security tasks running on ASP. With different considerations in terms of system overhead, complexity and performance, we also explore four typical system-level implementations for integrating the ASP to the security-first architecture. The first-generation ASP was designed and implemented based on the 40nm technology, and a security computer system was implemented based on it. Evaluations on this real hardware platform demonstrate that the security-first architecture can protect the system effectively with minor performance impacts on computing workloads.

Nonvolatile Associative Memory Design Based on Spintronic Synapses and CNTFET Neurons

Many advances have been made in developing bio-inspired intelligent systems for performing important tasks like pattern association, which cannot be performed effectively by the conventional computer architectures. This paper presents a novel nonvolatile associative memory based on spintronic synapses utilizing magnetic tunnel junction (MTJ) and carbon nanotube field-effect transistors (CNTFET)-based neurons. MTJs introduce fascinating features like reconfigurability, nonvolatility, and high endurance to the design, while CNTFETs compensate for the flaws of the conventional transistors in deep nanoscale nodes. The comprehensive simulations validate the functionality of the proposed synaptic cell, and neuron, even in the presence of major process variations. The application of the proposed synaptic cell and neuron in the hardware realization of multi-associative memories is also investigated. The simulation results indicate that the proposed hardware-based multi-associative memory performs similar to its ideal software-based counterpart with a less than 3 percent difference in the successful recall rate. It also noteworthy that since the input and output of the proposed design are logical ‘0’ and ‘1’, the proposed design does not need any extra component for voltage conversion.

Tetris: Using Software/Hardware Co-Design to Enable Handheld, Physics-Limited 3D Plane-Wave Ultrasound Imaging

High volume acquisition rates are imperative for certain medical ultrasound imaging applications, such as 3D elastography and 3D vector flow imaging. As ultrasound imaging transitions from 2D to 3D, the massive data bandwidth and billions of trigonometric operations required to reconstruct each volume leaves conventional computer architectures falling short. Despite recent algorithmic improvements, high-volume-rate ultrasound imaging remains computationally infeasible on known platforms. In this article, we expand our previous work on Tetris, a novel hardware accelerator for separable ultrasound beamforming that enables volume acquisition rates up to the physics limits of acoustic propagation delay. Through algorithmic and hardware optimizations, we enable an image reconstruction system design outclassing previously proposed accelerators in performance while lowering hardware complexity, storage, and power requirements. Tetris operates in a streaming fashion-without requiring on-chip storage of the entire receive signal-reconstructing volumes in real-time. For a representative imaging task, our proposed system generates physics-limited 13,000 volumes per second in a 2 watt power budget. The Tetris beamformer has an unprecedented power efficiency of 2.03 tera-beamforming operations per watt-an increase in efficiency of nearly 3× compared to the prior work.

Bayesian inference using stochastic logic: A study of buffering schemes for mitigating autocorrelation

Bayesian inference has become near ubiquitous in the design of algorithms for machine learning and autonomous robotic systems as this method provides a rigorous mathematical framework for the probabilistically handling of data with elements of uncertainty. As conventional computer architectures are inefficient in their implementation of probabilistic approaches to inference, stochastic computation has recently emerged as a viable alternative. Recent research has demonstrated that Bayes' rule can be directly implemented with a Muller C-element using stochastic computing. However, the switching inertia at the output due to the inherent memory effect in the C-element limits the accuracy of this approach. Previous methods for reducing this autocorrelation effect have ranged in complexity from counter-based regeneration to bit-reshuffling with memory buffers. Simplified buffering techniques that function independently of the state of C-element are proposed in this work and the effectiveness of the autocorrelation mitigation is evaluated. In addition, the use of multi-input C-elements are shown to add design flexibility for implementing Bayesian inference. Detailed numerical simulations and analysis of configurations that range from a simple cascade of gates to tree structures with large multi-input C-elements demonstrate the viability and limitations of the proposed simplified buffering approaches. These results are significant for their potential for enabling compact implementations of stochastic Bayesian approaches as control lines and random number generators can be shared across multiple C-elements.

A Neural Basis for the Implementation of Deep Learning and Arti cial Intelligence

One of the mathematical cornerstones of modern data ana-lytics is machine learning whereby we automatically learn subtle patterns which may be hidden in training data, we associate those patterns with outcomes and we apply these patterns to new and unseen data and make predictions about as yet unseen outcomes. This form of data analytics al-lows us to bring value to the huge volumes of data that is collected from people, from the environment, from commerce, from online activities, from scienti c experiments, from many other sources. The mathematical basis for this form of machine learning has led to tools like Support Vector Machines which have shown moderate e ectiveness and good e ciency in their implementation. Recently, however, these have been usurped by the emergence of deep learning based on convolutional neural networks. In this presentation we will examine the basis for why such deep net-works are remarkably successful and accurate, their similarity to ways in which the human brain is organised, and the challenges of implementing such deep networks on conventional computer architectures.

A high-reliability and low-power computing-in-memory implementation within STT-MRAM

In the conventional Von-Neumann computer architecture, more energy and time are consumed by the data transport, rather than the computation itself because of the limited bandwidth between the processor and memory. Computing-in-memory (CIM) is therefore proposed to effectively address the issue by moving some specified kinds of computation into the memory. It has been proposed for several decades, however, not really used when considering the reliability and cost. With the emergence of non-volatile memories, the CIM has regained interest to tackle the issue. In this paper, we implement a CIM scheme: ComRef (Complementary Reference) within STT-MRAM (Spin Transfer Torque Magnetic Random-Access Memory), and then compare its reliability and performance with the DualRef (Dual Reference) CIM implementation. Simulation results reveal that the ComRef obviously improves the reliability by decreasing 67.1% of the operation error rate and by increasing up to 57.4% of the sensing margin. It accelerates the bitwise logic operation with cutting down 20.8% (∼41.1 ps) of the operation delay. Most importantly, it is highly energy efficient by reducing 23.4% of the average dynamic energy and 65.6% of the average static power. The ComRef provides a pathway to implement high-reliability and low-power CIM paradigm within STT-MRAM.

Fully Functional Logic‐In‐Memory Operations Based on a Reconfigurable Finite‐State Machine Using a Single Memristor

AbstractMemristor offers a promising logic‐in‐memory (LIM) functionality to achieve the futuristic in‐memory computing machine, which may solve the problem of the “von Neumann bottleneck” in the conventional computer architecture. A sequential logic concept is capable of achieving LIM based on the finite‐state machine (FSM) using a single bipolar (BRS) or complementary resistive switching (CRS) memristor, where 14 of the 16 two‐input Boolean logic functions (XOR and XNOR are missing) are mapped between the resistance state and the terminal voltages. In this paper, a new FSM‐LIM concept based on a reconfigurable finite‐state machine (RFSM logic) is proposed, which is experimentally confirmed by a diode‐integrated single unipolar memristor. The scope of application of the proposed concept is further extended to three other asymmetric resistive switching devices, demonstrating the universality of the RFSM logic. With the use of different voltage conditions to denote logic input “1,” the function of FSM is reconfigured between the two state‐transition equations. Through the triggering of the two state‐transition equations alternatively, all the 16 Boolean logic functions can be achieved in three steps at most, without the assistance of reading operation. These correspond to the logical completeness and nonvolatility.

Memristive effects in oxygenated amorphous carbon nanodevices

Computing with resistive-switching (memristive) memory devices has shown much recent progress and offers an attractive route to circumvent the von-Neumann bottleneck, i.e. the separation of processing and memory, which limits the performance of conventional computer architectures. Due to their good scalability and nanosecond switching speeds, carbon-based resistive-switching memory devices could play an important role in this respect. However, devices based on elemental carbon, such as tetrahedral amorphous carbon or ta-C, typically suffer from a low cycling endurance. A material that has proven to be capable of combining the advantages of elemental carbon-based memories with simple fabrication methods and good endurance performance for binary memory applications is oxygenated amorphous carbon, or a-COx. Here, we examine the memristive capabilities of nanoscale a-COx devices, in particular their ability to provide the multilevel and accumulation properties that underpin computing type applications. We show the successful operation of nanoscale a-COx memory cells for both the storage of multilevel states (here 3-level) and for the provision of an arithmetic accumulator. We implement a base-16, or hexadecimal, accumulator and show how such a device can carry out hexadecimal arithmetic and simultaneously store the computed result in the self-same a-COx cell, all using fast (sub-10 ns) and low-energy (sub-pJ) input pulses.

In-Memory Processing Paradigm for Bitwise Logic Operations in STT–MRAM

In the current big data era, the memory wall issue between the processor and the memory becomes one of the most critical bottlenecks for conventional Von-Newman computer architecture. In-memory processing (IMP) or near-memory processing (NMP) paradigms have been proposed to address this problem by adding a small amount of processing units inside/near the memory. Unfortunately, although intensively studied, prior IMP/NMP platforms are practically unsuccessful because of the fabrication complexity and cost efficiency by integrating the processing units and memory on the same chip. Recently, emerging nonvolatile memories provide new possibility for efficiently implementing the IMP/NMP paradigm. In this paper, we propose a cost-efficient IMP/NMP solution in spin-transfer torque magnetic random access memory (STT–MRAM) without adding any processing units on the memory chip. The key idea behind the proposed IMP/NMP solution is to exploit the peripheral circuitry already existing inside memory (or with minimal changes) to perform bitwise logic operations. Such an IMP/NMP platform enables rather fast logic operations as the logic results can be obtained immediately through just a memory-like readout operation. Memory read and logics not, and/nand, and or/nor operations can be achieved and dynamically configured within the same STT–MRAM chip. Functionality and performance are evaluated with hybrid simulations under the 40 nm technology node.

Magnetoelectric Random Access Memory-Based Circuit Design by Using Voltage-Controlled Magnetic Anisotropy in Magnetic Tunnel Junctions

We introduce a magnetoelectric junction driven by voltage-controlled magnetic anisotropy (VCMA-MEJ) as a building block for a range of low-power memory applications. We present and discuss specifically two applications, magnetoelectric random access memory (MeRAM) and ternary content-addressable memory (TCAM). The MEJ differs from a magnetic tunnel junction (MTJ) in that electric field is used to induce switching in lieu of substantial current flow in MTJ. Electric field control of magnetism can dramatically enhance the performance of magnetic memory devices in terms of switching energy efficiency and switching speed. The development of such an energy-efficient and ultrafast memory has a potential to change the paradigm of a hierarchical memory system in the conventional computer architecture. By combining speed, low power, and high density, electric-field-controlled magnetic memory merges features of multiple separate memory technologies used in today's memory hierarchy. The performance of a VCMA-MEJs-based MeRAM, especially in the case of one access transistor associated with one MEJ (1T-1R) structure, is evaluated by comparing it with that of phase-change RAM, resistive RAM, and spin transfer torque RAM. MeRAM can achieve ultrafast switching (<1 ns), low switching energy (∼1 fJ), and compact cell size of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math>$6\;F^2$</tex-math></inline-formula> with a shared source region, as well as nonvolatility. For another application, we propose the VCMA-MEJ-based TCAM, which will be referred to as MeTCAM, consisting of 4T-2MEJs. Since MeTCAM fully exploits the low power and high density features of the VCMA effect both in write and search operation modes, it obtains a fast searching speed (0.2 ns) with the smallest cell area ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math>$44\;F^2 $</tex-math></inline-formula> ) compared to previous works.

Computer Architecture with Associative Processor Replacing Last-Level Cache and SIMD Accelerator

This study presents a computer architecture, where a last-level cache and a SIMD accelerator are replaced by an associative processor. Associative processor combines data storage and data processing, and functions as a massively parallel SIMD processor and a memory at the same time. An analytic performance model of this computer architecture is introduced. Comparative analysis supported by cycle-accurate simulation and emulation shows that this architecture may outperform a conventional computer architecture comprising a SIMD coprocessor and a shared last-level cache while consuming less power.

GPU-accelerated non-uniform fast Fourier transform-based compressive sensing spectral domain optical coherence tomography.

We implemented the graphics processing unit (GPU) accelerated compressive sensing (CS) non-uniform in k-space spectral domain optical coherence tomography (SD OCT). Kaiser-Bessel (KB) function and Gaussian function are used independently as the convolution kernel in the gridding-based non-uniform fast Fourier transform (NUFFT) algorithm with different oversampling ratios and kernel widths. Our implementation is compared with the GPU-accelerated modified non-uniform discrete Fourier transform (MNUDFT) matrix-based CS SD OCT and the GPU-accelerated fast Fourier transform (FFT)-based CS SD OCT. It was found that our implementation has comparable performance to the GPU-accelerated MNUDFT-based CS SD OCT in terms of image quality while providing more than 5 times speed enhancement. When compared to the GPU-accelerated FFT based-CS SD OCT, it shows smaller background noise and less side lobes while eliminating the need for the cumbersome k-space grid filling and the k-linear calibration procedure. Finally, we demonstrated that by using a conventional desktop computer architecture having three GPUs, real-time B-mode imaging can be obtained in excess of 30 fps for the GPU-accelerated NUFFT based CS SD OCT with frame size 2048(axial) × 1,000(lateral).